Datasheet > ZL30119_06

ZL30119_06

更新时间： 2024-11-21 03:08:35

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
28页	530K
描述
SONET/SDH OC-48/OC-192 Line Card Synchronizer

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数据手册

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ZL30119_06 数据手册

ZL30119

SONET/SDH

OC-48/OC-192 Line Card Synchronizer

Data Sheet

June 2006

A full Design Manual is available to qualified customers.

Ordering Information

please

send

ZL30119GGG

100 Pin CABGA

Trays

TimingandSync@Zarlink.com.

ZL30119GGG2 100 Pin CABGA*

*Pb Free Tin/Silver/Copper

Features

-40^oC to +85^oC

•

Synchronizes with standard telecom system

references and synthesizes a wide variety of

protected telecom line interface clocks that are

•

DPLL2 provides a comprehensive set of features

for generating derived output clocks and other

general purpose clocks

Provides 8 reference inputs which support clock

frequencies with any multiples of 8 kHz up to

77.76 MHz in addition to 2 kHz

compliant with Telcordia GR-253-CORE and ITU-T

G.813

•

Internal APLL provides standard output clock

frequencies up to 622.08 MHz that meet jitter

requirements for interfaces up to OC-192/STM-64

Programmable output synthesizers (P0, P1)

generate clock frequencies from any multiple of

8 kHz up to 77.76 MHz in addition to 2 kHz

•

Provides 3 sync inputs for output frame pulse

alignment

Generates several styles of output frame pulses

with selectable pulse width, polarity, and frequency

•

Provides two DPLLs which are independently

configurable through a serial peripheral interface

Configurable input to output delay, and output to

DPLL1 provides all the features necessary for

generating SONET/SDH compliant clocks including

automatic hitless reference switching, automatic

mode selection (locked, free-run, holdover), and

selectable loop bandwidth

output phase alignment

Flexible input reference monitoring automatically

disqualifies references based on frequency and

phase irregularities

•

Supports IEEE 1149.1 JTAG Boundary Scan

dpll2_ref

dpll1_holdover diff0_en diff1_en

trst_b tck tdi tms tdo

dpll1_hs_en

dpll1_lock

p0_clk0

p0_clk1

p0_fp0

p0_fp1

p1_clk0

p1_clk1

osco

osci

Master

Clock

IEEE 1449.1

JTAG

DPLL2

Synthesizer

ref

ref0

ref1

ref2

ref3

ref4

ref5

ref6

ref7

Synthesizer

ref7:0

diff0

diff1

sdh_clk0

sdh_clk1

sdh_fp0

sdh_fp1

SONET/SDH

APLL

DPLL1

sync0

sync1

sync2

sync2:0

sync

fb_clk

Feedback

fb_clk/fp

ref_&_sync_status

Reference

Monitors

Synthesizer

Controller &

int_b

SPI Interface

State Machine

sdh_filter filter_ref0 filter_ref1

sck

so cs_b

rst_b

dpll1_mod_sel1:0

Figure 1 - Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...28

中文翻译

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与ZL30119_06相关器件

型号	品牌	获取价格	描述	数据表
ZL30119GGG	ZARLINK	获取价格	Low Jitter Line Card Synchronizer
ZL30119GGG2	ZARLINK	获取价格	Low Jitter Line Card Synchronizer
ZL30120	ZARLINK	获取价格	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30120	MICROCHIP	获取价格	The ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides
ZL30120GGG	ZARLINK	获取价格	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30120GGG2	ZARLINK	获取价格	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30121	ZARLINK	获取价格	SONET/SDH Low Jitter System Synchronizer
ZL30121	MICROCHIP	获取价格	The ZL30121 SONET/SDH System Synchronizer is a highly integrated device that provides the
ZL30121GGG	ZARLINK	获取价格	SONET/SDH Low Jitter System Synchronizer
ZL30121GGG2	ZARLINK	获取价格	SONET/SDH Low Jitter System Synchronizer

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