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ZL30117GGG2 PDF预览

ZL30117GGG2

更新时间： 2024-11-21 03:08:35
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信集成电路异步传输模式ATM
页数 文件大小 规格书
24页 402K
描述
SONET/SDH OC-48/OC-192 Line Card Synchronizer

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中文翻译

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ZL30117GGG2 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：BGA, BGA64,8X8,40Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.79
应用程序：SONET;SDHJESD-30 代码：S-PBGA-B64
JESD-609代码：e1长度：9 mm
功能数量：1端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA64,8X8,40封装形状：SQUARE
封装形式：GRID ARRAY电源：1.8,3.3 V
认证状态：Not Qualified座面最大高度：1.72 mm
子类别：Other Telecom ICs标称供电电压：1.8 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM宽度：9 mm
Base Number Matches：1

ZL30117GGG2 数据手册

 浏览型号ZL30117GGG2的Datasheet PDF文件第2页浏览型号ZL30117GGG2的Datasheet PDF文件第3页浏览型号ZL30117GGG2的Datasheet PDF文件第4页浏览型号ZL30117GGG2的Datasheet PDF文件第5页浏览型号ZL30117GGG2的Datasheet PDF文件第6页浏览型号ZL30117GGG2的Datasheet PDF文件第7页 
ZL30117  
SONET/SDH  
OC-48/OC-192 Line Card Synchronizer  
Data Sheet  
June 2006  
A full Design Manual is available to qualified customers.  
Ordering Information  
To  
register,  
please  
send  
an  
email  
to  
ZL30117GGG  
64 Pin CABGA  
Trays  
Trays  
TimingandSync@Zarlink.com.  
ZL30117GGG2 64 Pin CABGA*  
*Pb Free Tin/Silver/Copper  
Features  
-40oC to +85oC  
•
Synchronizes with standard telecom system  
references and synthesizes a wide variety of  
protected telecom line interface clocks that are  
•
Provides 3 reference inputs which support clock  
frequencies with any multiples of 8 kHz up to  
77.76 MHz in addition to 2 kHz  
compliant with Telcordia GR-253-CORE and ITU-T  
G.813  
•
•
•
Internal APLL provides standard output clock  
frequencies up to 622.08 MHz that meet jitter  
requirements for interfaces up to OC-192/STM-64  
•
•
•
•
Provides 3 sync inputs for output frame pulse  
alignment  
Generates several styles of output frame pulses  
with selectable pulse width, polarity, and frequency  
Programmable output synthesizer generates clock  
frequencies from any multiple of 8 kHz up to  
77.76 MHz in addition to 2 kHz  
Configurable input to output delay, and output to  
output phase alignment  
Flexible input reference monitoring automatically  
disqualifies references based on frequency and  
phase irregularities  
Digital Phase Locked-Loop (DPLL) provides all the  
features necessary for generating SONET/SDH  
compliant clocks including automatic hitless  
reference switching, automatic mode selection  
(locked, free-run, holdover), and selectable loop  
bandwidth  
•
Supports IEEE 1149.1 JTAG Boundary Scan  
dpll_holdover  
dpll_lock  
diff_en  
trst_b tck tdi tms tdo  
osco  
osci  
Master  
Clock  
IEEE 1449.1  
JTAG  
ref0  
ref1  
ref2  
ref2:0  
ref  
diff_clk_p/n  
SONET/SDH  
sdh_clk  
sdh_fp  
APLL  
DPLL  
p_clk  
p_fp  
Programmable  
Synthesizer  
sync0  
sync1  
sync2  
sync2:0  
sync  
ref_&_sync_status  
Reference  
Monitors  
Controller &  
int_b  
SPI Interface  
State Machine  
sdh_filter filter_ref0 filter_ref1  
sck  
si  
so cs_b  
rst_b  
dpll_mod_sel  
Figure 1 - Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.  
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中文翻译

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