Datasheet > ZL30117

ZL30117

更新时间： 2024-11-22 14:55:11

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
24页	262K
描述
The ZL30117 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing an

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ZL30117 数据手册

ZL30117

SONET/SDH

OC-48/OC-192 Line Card Synchronizer

Data Sheet

June 2006

Features

Ordering Information

•

Synchronizes with standard telecom system

references and synthesizes a wide variety of

protected telecom line interface clocks that are

compliant with Telcordia GR-253-CORE and ITU-T

G.813

ZL30117GGG

64 Pin CABGA

Trays

ZL30117GGG2 64 Pin CABGA*

*Pb Free Tin/Silver/Copper

-40^oC to +85^oC

•

Internal APLL provides standard output clock

frequencies up to 622.08 MHz that meet jitter

requirements for interfaces up to OC-192/STM-64

•

Provides 3 sync inputs for output frame pulse

alignment

Programmable output synthesizer generates clock

frequencies from any multiple of 8 kHz up to

77.76 MHz in addition to 2 kHz

Generates several styles of output frame pulses

with selectable pulse width, polarity, and frequency

Configurable input to output delay, and output to

output phase alignment

Digital Phase Locked-Loop (DPLL) provides all the

features necessary for generating SONET/SDH

compliant clocks including automatic hitless

reference switching, automatic mode selection

(locked, free-run, holdover), and selectable loop

bandwidth

Flexible input reference monitoring automatically

disqualifies references based on frequency and

phase irregularities

•

Supports IEEE 1149.1 JTAG Boundary Scan

•

Provides 3 reference inputs which support clock

frequencies with any multiples of 8 kHz up to

77.76 MHz in addition to 2 kHz

dpll_holdover

dpll_lock

diff_en

trst_b tck tdi tms tdo

osco

osci

Master

Clock

IEEE 1449.1

JTAG

ref0

ref1

ref2

ref2:0

ref

diff_clk_p/n

SONET/SDH

sdh_clk

sdh_fp

APLL

DPLL

p_clk

p_fp

Programmable

Synthesizer

sync0

sync1

sync2

sync2:0

sync

ref_&_sync_status

Reference

Monitors

Controller &

State Machine

int_b

SPI Interface

sdh_filter filter_ref0 filter_ref1

sck

so cs_b

rst_b

dpll_mod_sel

Figure 1 - Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...24

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与ZL30117相关器件

型号	品牌	获取价格	描述	数据表
ZL30117GGG	ZARLINK	获取价格	SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30117GGG2	ZARLINK	获取价格	SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30119	ZARLINK	获取价格	Low Jitter Line Card Synchronizer
ZL30119	MICROCHIP	获取价格	The ZL30119 SONET/SDH Line Card Synchronizer is a highly integrated device that provides t
ZL30119_06	ZARLINK	获取价格	SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30119GGG	ZARLINK	获取价格	Low Jitter Line Card Synchronizer
ZL30119GGG2	ZARLINK	获取价格	Low Jitter Line Card Synchronizer
ZL30120	ZARLINK	获取价格	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30120	MICROCHIP	获取价格	The ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides
ZL30120GGG	ZARLINK	获取价格	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer

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