Datasheet > ZL30112

ZL30112

更新时间： 2024-09-29 14:54:15

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
23页	349K
描述
The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides

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ZL30112 数据手册

ZL30112

SLIC/CODEC DPLL

Data Sheet

November 2009

Features

•

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or

19.44 MHz input

Ordering Information

ZL30112LDG1

32 Pin QFN*

Trays, Bake

& Drypack

Provides 2.048 MHz and 8.192 MHz output clocks

and an 8 kHz framing pulse

*Pb Free Matte Tin

Automatic entry and exit from freerun mode on

reference fail

-40°C to +85°C

•

Provides DPLL lock and reference fail indication

Description

DPLL bandwidth of 29 Hz for all rates of input

references

The ZL30112 SLIC/CODEC DPLL contains a digital

phase-locked loop (DPLL), which provides timing and

synchronization for SLIC/CODEC devices.

•

Less than 0.6 nsec_ppintrinsic jitter on all output

clocks

The ZL30112 generates TDM clock and framing

signals that are phase locked to the input reference.

It helps ensure system reliability by monitoring its

reference for stability and by maintaining stable

output clocks during short periods when the

reference is unavailable.

20 MHz external master clock source: clock

oscillator or crystal

Simple hardware control interface

Applications

•

Synchronizer for POTS SLIC/CODEC

Rate convert NTR 8 kHz or GPON physical interface

clock to TDM clock

REF_FAIL

LOCK

C2o

REF

C8o

DPLL

F8ko

Reference

Monitor

Mode

Control

RST

State Machine

OSCi

Master

Clock

OSCo

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...23

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