Datasheet > ZL30111

ZL30111

更新时间： 2023-12-06 20:07:37

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
21页	247K
描述
The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing

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ZL30111 数据手册

ZL30111

POTS Line Card PLL

Data Sheet

January 2007

Features

•

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or

Ordering Information

64 Pin TQFP Trays, Bake & Drypack

ZL30111QDG1 64 Pin TQFP* Trays, Bake & Drypack

*Pb Free Matte Tin

19.44 MHz input

ZL30111QDG

•

Provides a range of clock outputs: 2.048 MHz,

4.096 MHz and 8.192 MHz

Provides 2 styles of 8 kHz framing pulses

•

-40°C to +85°C

Automatic entry and exit from freerun mode on

reference fail

Provides DPLL lock and reference fail indication

Applications

•

Synchronizer for POTS line cards

•

Rate convert NTR 8kHz or GPON physical

interface clock to TDM clock

DPLL bandwidth of 922 Hz for all rates of input

reference and 58 Hz for an 8 kHz input reference

•

Less than 0.6 ns_ppintrinsic jitter on all output clocks

Description

The ZL30111 POTS line card PLL contains a digital

phase-locked loop (DPLL), which provides timing and

synchronization for SLIC/CODEC devices.

20 MHz external master clock source: clock

oscillator or crystal

•

Simple hardware control interface

The ZL30111 generates TDM clock and framing

signals that are phase locked to the input reference.

It helps ensure system reliability by monitoring its

reference for stability and by maintaining stable

output clocks during short periods when the

reference is unavailable.

REF_FAIL

LOCK

C2o

REF

DPLL

Reference

Monitor

Mode

Control

RST

State Machine

OSCi

OSCo

Master

Clock

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...21

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