5秒后页面跳转
ZL30110LDE1 PDF预览

ZL30110LDE1

更新时间: 2024-11-21 03:08:35
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信集成电路电信电路
页数 文件大小 规格书
21页 293K
描述
Telecom Rate Conversion DPLL

ZL30110LDE1 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:HVQCCN, LCC32,.2SQ,20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.65
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm功能数量:1
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC32,.2SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
电源:3.3 V认证状态:Not Qualified
座面最大高度:0.9 mm子类别:Other Telecom ICs
最大压摆率:0.115 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:5 mm
Base Number Matches:1

ZL30110LDE1 数据手册

 浏览型号ZL30110LDE1的Datasheet PDF文件第2页浏览型号ZL30110LDE1的Datasheet PDF文件第3页浏览型号ZL30110LDE1的Datasheet PDF文件第4页浏览型号ZL30110LDE1的Datasheet PDF文件第5页浏览型号ZL30110LDE1的Datasheet PDF文件第6页浏览型号ZL30110LDE1的Datasheet PDF文件第7页 
ZL30110  
Telecom Rate Conversion DPLL  
Data Sheet  
November 2006  
Features  
Ordering Information  
Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or  
16.384 MHz  
ZL30110LDE  
ZL30110LDE1  
32 Pin QFN  
32 Pin QFN*  
Tubes Bake & Dry Pack  
Tubes Bake & Dry Pack  
Provides a range of output clocks:  
*Pb Free Matte Tin  
65.536 MHz TDM clock locked to the input  
reference  
-40°C to +85°C  
General purpose 25 MHz fan-out to 6 outputs  
locked to the external crystal or oscillator  
Applications  
Clock rate conversion PLL for Telecommunication  
General purpose 125 MHz and 66 MHz or  
100 MHz locked to the external crystal or  
oscillator  
Equipment  
Small/Medium Enterprise Router / Gateway  
Broadband access (xPON/xDSL) CPE gateway  
Provides DPLL lock and reference fail indication  
Automatic free run mode on reference fail  
DPLL bandwidth of 922 Hz for all rates of input  
reference and 58 Hz for an 8 kHz input reference  
Description  
The ZL30110 clock rate conversion digital phase-  
locked loop (DPLL) provides accurate and reliable  
frequency conversion.  
Less than 5 psecrms on 25 MHz outputs, and less  
than 0.6 nspp intrinsic jitter on the all other outputs  
Minimal input to output and output to output skew  
The ZL30110 generates a range of clocks that are  
either locked to the input reference or locked to the  
external crystal or oscillator.  
25 MHz external master clock source: clock  
oscillator or crystal  
Simple hardware control interface  
In the locked mode, the reference input is continuously  
monitored for a failure condition. In the event of a  
failure, the DPLL continues to provide a stable free  
running clock ensuring system reliability.  
REF_FAIL  
LOCK  
REF  
Frequency  
C65o  
DPLL  
Synthesizer  
Reference  
Monitor  
State Machine  
RST  
Select MUX  
OUT_SEL  
C100/66o  
C125o  
APLL  
APLL  
OSCi  
Master  
Clock  
OSCo  
6 X C25o  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.  

与ZL30110LDE1相关器件

型号 品牌 获取价格 描述 数据表
ZL30110LDF1 ZARLINK

获取价格

Telecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32
ZL30110LDG1 MICROSEMI

获取价格

Telecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32
ZL30111 ZARLINK

获取价格

POTS Line Card PLL
ZL30111 MICROCHIP

获取价格

The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides
ZL30111QDG ZARLINK

获取价格

POTS Line Card PLL
ZL30111QDG1 ZARLINK

获取价格

POTS Line Card PLL
ZL30112 MICROCHIP

获取价格

The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which p
ZL30116 ZARLINK

获取价格

SONET/SDH OC-48/OC-192 System Synchronizer
ZL30116GGG ZARLINK

获取价格

SONET/SDH OC-48/OC-192 System Synchronizer
ZL30116GGG2 ZARLINK

获取价格

SONET/SDH OC-48/OC-192 System Synchronizer