Datasheet > ZL30110LDE

ZL30110LDE

更新时间： 2024-11-21 03:08:35

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		电信
页数	文件大小	规格书
21页	293K
描述
Telecom Rate Conversion DPLL

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ZL30110LDE 数据手册

ZL30110

Telecom Rate Conversion DPLL

Data Sheet

November 2006

Features

Ordering Information

•

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or

16.384 MHz

ZL30110LDE

ZL30110LDE1

32 Pin QFN

32 Pin QFN*

Tubes Bake & Dry Pack

•

Provides a range of output clocks:

*Pb Free Matte Tin

•

65.536 MHz TDM clock locked to the input

reference

-40°C to +85°C

General purpose 25 MHz fan-out to 6 outputs

locked to the external crystal or oscillator

Applications

•

Clock rate conversion PLL for Telecommunication

General purpose 125 MHz and 66 MHz or

100 MHz locked to the external crystal or

oscillator

Equipment

•

Small/Medium Enterprise Router / Gateway

Broadband access (xPON/xDSL) CPE gateway

•

Provides DPLL lock and reference fail indication

Automatic free run mode on reference fail

DPLL bandwidth of 922 Hz for all rates of input

reference and 58 Hz for an 8 kHz input reference

Description

The ZL30110 clock rate conversion digital phase-

locked loop (DPLL) provides accurate and reliable

frequency conversion.

•

Less than 5 psec_rmson 25 MHz outputs, and less

than 0.6 nspp intrinsic jitter on the all other outputs

•

Minimal input to output and output to output skew

The ZL30110 generates a range of clocks that are

either locked to the input reference or locked to the

external crystal or oscillator.

25 MHz external master clock source: clock

oscillator or crystal

•

Simple hardware control interface

In the locked mode, the reference input is continuously

monitored for a failure condition. In the event of a

failure, the DPLL continues to provide a stable free

running clock ensuring system reliability.

REF_FAIL

LOCK

REF

Frequency

C65o

DPLL

Synthesizer

Reference

Monitor

State Machine

RST

Select MUX

OUT_SEL

C100/66o

C125o

APLL

OSCi

Master

Clock

OSCo

6 X C25o

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...21

中文翻译

下载PDF

与ZL30110LDE相关器件

型号	品牌	获取价格	描述	数据表
ZL30110LDE1	ZARLINK	获取价格	Telecom Rate Conversion DPLL
ZL30110LDF1	ZARLINK	获取价格	Telecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32
ZL30110LDG1	MICROSEMI	获取价格	Telecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32
ZL30111	ZARLINK	获取价格	POTS Line Card PLL
ZL30111	MICROCHIP	获取价格	The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides
ZL30111QDG	ZARLINK	获取价格	POTS Line Card PLL
ZL30111QDG1	ZARLINK	获取价格	POTS Line Card PLL
ZL30112	MICROCHIP	获取价格	The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which p
ZL30116	ZARLINK	获取价格	SONET/SDH OC-48/OC-192 System Synchronizer
ZL30116GGG	ZARLINK	获取价格	SONET/SDH OC-48/OC-192 System Synchronizer