ZL30110
Telecom Rate Conversion DPLL
Data Sheet
November 2006
Features
Ordering Information
•
Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
16.384 MHz
ZL30110LDE
ZL30110LDE1
32 Pin QFN
32 Pin QFN*
Tubes Bake & Dry Pack
Tubes Bake & Dry Pack
•
Provides a range of output clocks:
*Pb Free Matte Tin
•
•
•
65.536 MHz TDM clock locked to the input
reference
-40°C to +85°C
General purpose 25 MHz fan-out to 6 outputs
locked to the external crystal or oscillator
Applications
•
Clock rate conversion PLL for Telecommunication
General purpose 125 MHz and 66 MHz or
100 MHz locked to the external crystal or
oscillator
Equipment
•
•
Small/Medium Enterprise Router / Gateway
Broadband access (xPON/xDSL) CPE gateway
•
•
•
Provides DPLL lock and reference fail indication
Automatic free run mode on reference fail
DPLL bandwidth of 922 Hz for all rates of input
reference and 58 Hz for an 8 kHz input reference
Description
The ZL30110 clock rate conversion digital phase-
locked loop (DPLL) provides accurate and reliable
frequency conversion.
•
Less than 5 psecrms on 25 MHz outputs, and less
than 0.6 nspp intrinsic jitter on the all other outputs
•
•
Minimal input to output and output to output skew
The ZL30110 generates a range of clocks that are
either locked to the input reference or locked to the
external crystal or oscillator.
25 MHz external master clock source: clock
oscillator or crystal
•
Simple hardware control interface
In the locked mode, the reference input is continuously
monitored for a failure condition. In the event of a
failure, the DPLL continues to provide a stable free
running clock ensuring system reliability.
REF_FAIL
LOCK
REF
Frequency
C65o
DPLL
Synthesizer
Reference
Monitor
State Machine
RST
Select MUX
OUT_SEL
C100/66o
C125o
APLL
APLL
OSCi
Master
Clock
OSCo
6 X C25o
Figure 1 - Functional Block Diagram
1
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Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.