Datasheet > ZL30110

ZL30110

更新时间： 2023-12-06 20:09:50

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
22页	320K
描述
The ZL30110 clock rate conversion digital phase-locked loop (DPLL) provides accurate and reliable

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ZL30110 数据手册

ZL30110

Telecom Rate Conversion DPLL

Data Sheet

May 2009

Features

Ordering Information

•

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or

16.384 MHz

ZL30110LDE

ZL30110LDG1

ZL30110LDF1

32 Pin QFN

32 Pin QFN*

Tubes, Bake & Dry Pack

Trays, Bake & Dry Pack

Tape & Reel

•

Provides a range of output clocks:

•

65.536 MHz TDM clock locked to the input

reference

*Pb Free Matte Tin

-40°C to +85°C

General purpose 25 MHz fan-out to 6 outputs

locked to the external crystal or oscillator

Applications

•

Clock rate conversion PLL for Telecommunication

General purpose 125 MHz and 66 MHz or

100 MHz locked to the external crystal or

oscillator

Equipment

•

Small/Medium Enterprise Router / Gateway

Broadband access (xPON/xDSL) CPE gateway

•

Provides DPLL lock and reference fail indication

Automatic free run mode on reference fail

Description

DPLL bandwidth of 922 Hz for all rates of input

reference and 58 Hz for an 8 kHz input reference

The ZL30110 clock rate conversion digital phase-

locked loop (DPLL) provides accurate and reliable

frequency conversion.

•

Less than 5 psec_rmson 25 MHz outputs, and less

than 0.6 nspp intrinsic jitter on the all other outputs

•

Minimal input to output and output to output skew

The ZL30110 generates a range of clocks that are

either locked to the input reference or locked to the

external crystal or oscillator.

25 MHz external master clock source: clock

oscillator or crystal

•

Simple hardware control interface

In the locked mode, the reference input is continuously

monitored for a failure condition. In the event of a

failure, the DPLL continues to provide a stable free

running clock ensuring system reliability.

REF_FAIL

LOCK

REF

Frequency

Synthesizer

C65o

DPLL

Reference

Monitor

State Machine

RST

Select MUX

OUT_SEL

C100/66o

C125o

APLL

OSCi

OSCo

Master

Clock

6 X C25o

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...22

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与ZL30110相关器件

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ZL30110LDG1	MICROSEMI	获取价格	Telecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32
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