Datasheet > ZL30109_05

ZL30109_05

更新时间： 2024-02-17 06:41:01

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
37页	787K
描述
DS1/E1 System Synchronizer with

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数据手册

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ZL30109_05 数据手册

ZL30109

DS1/E1 System Synchronizer with

19.44 MHz Output

Data Sheet

November 2005

Features

•

Supports Telcordia GR-1244-CORE Stratum 4 and

Ordering Information

Stratum 4E

ZL30109QDG 64 Pin TQFP Trays, Bake & Drypack

ZL30109QDG1 64 pin TQFP* Trays, Bake & Drypack

Supports ITU-T G.823 and G.824 for 2048 kbit/s and

1544 kbit/s interfaces

Supports ANSI T1.403 and ETSI ETS 300 011 for

ISDN primary rate interfaces

*Pb Free Matte Tin

-40°C to +85°C

•

Simple hardware control interface

•

Less than 24 ps_rmsintrinsic jitter on the

19.44 MHz output clock, compliant with OC-3 and

STM-1 jitter specifications

Accepts two input references and synchronizes to

any combination of 2 kHz, 8 kHz, 1.544 MHz,

2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz

inputs

•

Less than 0.6 ns_ppintrinsic jitter on all output

clocks

•

Provides a range of clock outputs: 1.544 MHz,

2.048 MHz, 16.384 MHz, 19.44 MHz and either

4.096 MHz and 8.192 MHz or 32.768 MHz and

65.536 MHz

External master clock source: clock oscillator or

crystal

Applications

•

Hitless reference switching between any

Synchronization and timing control for DSLAM,

Gateway and PBX systems that require Stratum

4/4E timing

Line Card synchronization for SDH/PDH

applications

combination of valid input reference frequencies

Provides 5 styles of 8 kHz framing pulses and a

2 kHz multi-frame pulse

•

Holdover frequency accuracy of 1.5 x 10^-7

Lock, Holdover and selectable Out of Range

indication

Clock and frame pulse source for ST-BUS, GCI

and other time division multiplex (TDM) buses

•

Selectable loop filter bandwidth of 1.8 Hz or 922 Hz

TIE_CLR

OSCi OSCo

Master Clock

BW_SEL

OUT_SEL

LOCK

C2o

Virtual

C4/C65o

C8/C32o

C16o

REF0

REF1

TIE

Reference

MUX

Corrector

Circuit

DPLL

Synthesizer

F4/F65o

F8/F32o

F16o

REF_FAIL0

REF_FAIL1

TIE

Reference

Monitor

Mode

C1.5o

Corrector

Enable

DS1

Control

Synthesizer

OOR_SEL

C19o

F2ko

SONET/SDH

Synthesizer

Feedback

Frequency

Select

REF_SEL

RST

MUX

State Machine

IEEE

TRST

1149.1a

MODE_SEL1:0

HOLDOVER

HMS

TCK TDI TMS TDO

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...37

中文翻译

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与ZL30109_05相关器件

型号	品牌	获取价格	描述	数据表
ZL30109QDG	ZARLINK	获取价格	DS1/E1 System Synchronizer with 19.44 MHz Output
ZL30109QDG1	ZARLINK	获取价格	DS1/E1 System Synchronizer with
ZL30110	ZARLINK	获取价格	Telecom Rate Conversion DPLL
ZL30110	MICROCHIP	获取价格	The ZL30110 clock rate conversion digital phase-locked loop (DPLL) provides accurate and r
ZL30110LDE	ZARLINK	获取价格	Telecom Rate Conversion DPLL
ZL30110LDE1	ZARLINK	获取价格	Telecom Rate Conversion DPLL
ZL30110LDF1	ZARLINK	获取价格	Telecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32
ZL30110LDG1	MICROSEMI	获取价格	Telecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32
ZL30111	ZARLINK	获取价格	POTS Line Card PLL
ZL30111	MICROCHIP	获取价格	The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides

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