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ZL30108LDG1 PDF预览

ZL30108LDG1

更新时间： 2024-11-21 20:10:31
品牌 Logo 应用领域
美国微芯 - MICROCHIP ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
57页 691K
描述
ATM/SONET/SDH Support Circuit, 1-Func

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ZL30108LDG1 技术参数

生命周期：Active包装说明：HVQCCN,
Reach Compliance Code：compliantFactory Lead Time：7 weeks
风险等级：5.79JESD-30 代码：S-XQCC-N32
长度：5 mm功能数量：1
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度：1 mm
标称供电电压：1.8 V表面贴装：YES
电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：5 mm
Base Number Matches：1

ZL30108LDG1 数据手册

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ZL30108  
SONET/SDH  
Network Interface DPLL  
Data Sheet  
May 2009  
Features  
Ordering Information  
•
Supports output wander and jitter generation  
specifications for GR-253-CORE OC-3 and G.813  
STM-1 SONET/SDH interfaces  
ZL30108LDA  
ZL30108LDG1  
32 Pin QFN  
32 Pin QFN* Trays, Bake & Drypack  
*Pb Free Matte Tin  
Tubes, Bake & Drypack  
•
Accepts two input references and synchronizes to  
any combination of 2 kHz, 8 kHz, 1.544 MHz,  
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz  
inputs  
-40°C to +85°C  
Applications  
•
•
Provides a 19.44 MHz (SONET/SDH) clock output  
•
Line card synchronization for SONET/SDH  
systems  
Provides an 8 kHz framing pulse and a 2 kHz  
multi-frame pulse  
Description  
•
•
•
Provides automatic entry into Holdover and return  
from Holdover  
The ZL30108 SONET/SDH network interface digital  
phase-locked loop (DPLL) provides timing and  
synchronization for SONET/SDH network interface  
cards.  
Hitless reference switching between any  
combination of valid input reference frequencies  
Provides lock and accurate reference fail  
indication  
The ZL30108 generates a SONET/SDH clock and  
framing signals that are phase locked to one of two  
backplane or network references. It helps ensure  
system reliability by monitoring its references for  
frequency accuracy and stability and by maintaining  
tight phase alignment between the input reference  
clock and clock outputs.  
•
•
Loop filter bandwidth of 29 Hz or 14 Hz  
Less than 24 psrms intrinsic jitter on the 19.44 MHz  
output clock, compliant with GR-253-CORE OC-3  
and G.813 STM-1 specifications  
•
•
•
Less than 0.5 nspp intrinsic jitter on output frame  
pulses  
The ZL30108 output clock’s wander and jitter  
generation are compliant with GR-253-CORE OC-3  
and G.813 STM-1 specifications.  
External master clock source: clock oscillator or  
crystal  
Simple hardware control interface  
OSCi OSCo TIE_CLR  
Master Clock  
LOCK  
Virtual  
Reference  
REF0  
REF1  
C19o  
F8ko  
TIE  
MUX  
Corrector  
Frequency  
Synthesizer  
Circuit  
DPLL  
F2ko  
REF_FAIL0  
REF_FAIL1  
OOR_SEL  
REF_SEL  
TIE  
Corrector  
Enable  
Reference  
Monitor  
Mode  
Control  
RST  
State Machine  
Frequency  
Select  
MODE_SEL  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2004-2009, Zarlink Semiconductor Inc. All Rights Reserved.  
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