ZL30108
SONET/SDH
Network Interface DPLL
Data Sheet
October 2004
Features
Ordering Information
•
Supports output wander and jitter generation
specifications for GR-253-CORE OC-3 and G.813
STM-1 SONET/SDH interfaces
ZL30108LDA
32 pin QFN
-40°C to +85°C
•
Accepts two input references and synchronizes to
any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
Applications
•
Line card synchronization for SONET/SDH
•
•
Provides a 19.44 MHz (SONET/SDH) clock output
systems
Provides an 8 kHz framing pulse and a 2 kHz
multi-frame pulse
Provides automatic entry into Holdover and return
from Holdover
Description
•
The ZL30108 SONET/SDH network interface digital
phase-locked loop (DPLL) provides timing and
synchronization for SONET/SDH network interface
cards.
•
•
Hitless reference switching
Provides lock and accurate reference fail
indication
The ZL30108 generates a SONET/SDH clock and
framing signals that are phase locked to one of two
backplane or network references. It helps ensure
system reliability by monitoring its references for
frequency accuracy and stability and by maintaining
tight phase alignment between the input reference
clock and clock outputs.
•
•
Loop filter bandwidth of 29 Hz or 14 Hz
Less than 24 psrms intrinsic jitter on the 19.44 MHz
output clock, compliant with GR-253-CORE OC-3
and G.813 STM-1 specifications
•
•
•
Less than 0.5 nspp intrinsic jitter on output frame
pulses
The ZL30108 output clock’s wander and jitter
generation are compliant with GR-253-CORE OC-3
and G.813 STM-1 specifications.
External master clock source: clock oscillator or
crystal
Simple hardware control interface
OSCi OSCo TIE_CLR
Master Clock
LOCK
Virtual
REF0
C19o
F8ko
F2ko
TIE
Reference
MUX
Corrector
Circuit
Frequency
REF1
DPLL
Synthesizer
REF_FAIL0
REF_FAIL1
TIE
Reference
Monitor
Corrector
Enable
OOR_SEL
REF_SEL
Mode
Control
RST
MODE_SEL
State Machine
Frequency
Select
Figure 1 - Functional Block Diagram
1
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Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.