5秒后页面跳转
ZL30108 PDF预览

ZL30108

更新时间: 2024-11-03 14:55:35
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
57页 691K
描述
The?ZL30108?SONET/SDH network interface digital phase-locked loop (DPLL) provides timing and synch

ZL30108 数据手册

 浏览型号ZL30108的Datasheet PDF文件第2页浏览型号ZL30108的Datasheet PDF文件第3页浏览型号ZL30108的Datasheet PDF文件第4页浏览型号ZL30108的Datasheet PDF文件第5页浏览型号ZL30108的Datasheet PDF文件第6页浏览型号ZL30108的Datasheet PDF文件第7页 
ZL30108  
SONET/SDH  
Network Interface DPLL  
Data Sheet  
May 2009  
Features  
Ordering Information  
Supports output wander and jitter generation  
specifications for GR-253-CORE OC-3 and G.813  
STM-1 SONET/SDH interfaces  
ZL30108LDA  
ZL30108LDG1  
32 Pin QFN  
32 Pin QFN* Trays, Bake & Drypack  
*Pb Free Matte Tin  
Tubes, Bake & Drypack  
Accepts two input references and synchronizes to  
any combination of 2 kHz, 8 kHz, 1.544 MHz,  
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz  
inputs  
-40°C to +85°C  
Applications  
Provides a 19.44 MHz (SONET/SDH) clock output  
Line card synchronization for SONET/SDH  
systems  
Provides an 8 kHz framing pulse and a 2 kHz  
multi-frame pulse  
Description  
Provides automatic entry into Holdover and return  
from Holdover  
The ZL30108 SONET/SDH network interface digital  
phase-locked loop (DPLL) provides timing and  
synchronization for SONET/SDH network interface  
cards.  
Hitless reference switching between any  
combination of valid input reference frequencies  
Provides lock and accurate reference fail  
indication  
The ZL30108 generates a SONET/SDH clock and  
framing signals that are phase locked to one of two  
backplane or network references. It helps ensure  
system reliability by monitoring its references for  
frequency accuracy and stability and by maintaining  
tight phase alignment between the input reference  
clock and clock outputs.  
Loop filter bandwidth of 29 Hz or 14 Hz  
Less than 24 psrms intrinsic jitter on the 19.44 MHz  
output clock, compliant with GR-253-CORE OC-3  
and G.813 STM-1 specifications  
Less than 0.5 nspp intrinsic jitter on output frame  
pulses  
The ZL30108 output clock’s wander and jitter  
generation are compliant with GR-253-CORE OC-3  
and G.813 STM-1 specifications.  
External master clock source: clock oscillator or  
crystal  
Simple hardware control interface  
OSCi OSCo TIE_CLR  
Master Clock  
LOCK  
Virtual  
Reference  
REF0  
REF1  
C19o  
F8ko  
TIE  
MUX  
Corrector  
Frequency  
Synthesizer  
Circuit  
DPLL  
F2ko  
REF_FAIL0  
REF_FAIL1  
OOR_SEL  
REF_SEL  
TIE  
Corrector  
Enable  
Reference  
Monitor  
Mode  
Control  
RST  
State Machine  
Frequency  
Select  
MODE_SEL  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2004-2009, Zarlink Semiconductor Inc. All Rights Reserved.  

与ZL30108相关器件

型号 品牌 获取价格 描述 数据表
ZL30108_06 ZARLINK

获取价格

SONET/SDH Network Interface DPLL
ZL30108LDA ZARLINK

获取价格

Network Interface DPLL
ZL30108LDA XILINX

获取价格

ATM/SONET/SDH SUPPORT CIRCUIT, QCC32, 5 X 5 MM, MO-220, QFN-32
ZL30108LDE1 ZARLINK

获取价格

SONET/SDH Network Interface DPLL
ZL30108LDG1 XILINX

获取价格

ATM/SONET/SDH SUPPORT CIRCUIT, QCC32, 5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE,
ZL30108LDG1 MICROCHIP

获取价格

ATM/SONET/SDH Support Circuit, 1-Func
ZL30108LDG1 ZARLINK

获取价格

Support Circuit, 1-Func, CMOS, 5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-220,
ZL30109 ZARLINK

获取价格

DS1/E1 System Synchronizer with 19.44 MHz Output
ZL30109 MICROCHIP

获取价格

The ZL30109 DS1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which
ZL30109_05 ZARLINK

获取价格

DS1/E1 System Synchronizer with