ZL30107

更新时间： 2024-11-02 03:08:35

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		以太网
页数	文件大小	规格书
6页	186K
描述
GbE Line Card Synchronizer

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数据手册

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ZL30107 数据手册

ZL30107

GbE Line Card Synchronizer

Shortform Data Sheet

March 2007

A full Data Sheet is available to qualified customers. To

Ordering Information

please

send

ZL30107GGG

64 Pin CABGA

Trays

TimingandSync@zarlink.com.

ZL30107GGG2 64 Pin CABGA*

*Pb Free Tin/Silver/Copper

Features

-40^oC to +85^oC

•

Single chip low cost solution for synchronizing an

Ethernet PHY to a standard telecom clock

•

Configurable to accept a 25 MHz input reference

Generates an IEEE 802.3 jitter compliant 25 MHz

Gigabit Ethernet output clock

Supports three modes of operation:

Asynchronous Freerun, Synchronous, and

Asynchronous Holdover

Automatic entry into Asynchronous Holdover

mode when all input references fail

Input reference is manually selectable through the

serial (SPI) interface

•

Defaults in Asynchronous Freerun mode

•

Hitless input reference switching

Lock indicator pin

In Asynchronous Freerun mode, the DPLL

generates an output clock with a frequency

accuracy equal to frequency accuracy of the

external crystal oscillator (XO) or a low cost

crystal (XTAL)

Input reference status monitors

Programmable loop bandwidth of 14 Hz, 28 Hz, or

890 Hz

•

In Synchronous mode, the DPLL automatically

synchronizes to one of a pre-defined set of

frequencies including 2 kHz, 8 kHz, 64 kHz,

1.544 MHz, 2.048 MHz, 6.48 MHz, 8.192 MHz,

16.384 MHz, 19.44 MHz, 38.88 MHz, 77.76 MHz.

Applications

•

Ethernet Line Cards Supporting Synchronous

Transmission

X1/CLK X2

LOCK

REF0

REF1

REF2

DPLL

CLK

APLL

uP I/F

Figure 1 - Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6

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与ZL30107相关器件

型号	品牌	获取价格	描述	数据表
ZL30107GGG	ZARLINK	获取价格	GbE Line Card Synchronizer
ZL30107GGG2	ZARLINK	获取价格	GbE Line Card Synchronizer
ZL30108	ZARLINK	获取价格	Network Interface DPLL
ZL30108	MICROCHIP	获取价格	The?ZL30108?SONET/SDH network interface digital phase-locked loop (DPLL) provides timing a
ZL30108_06	ZARLINK	获取价格	SONET/SDH Network Interface DPLL
ZL30108LDA	ZARLINK	获取价格	Network Interface DPLL
ZL30108LDA	XILINX	获取价格	ATM/SONET/SDH SUPPORT CIRCUIT, QCC32, 5 X 5 MM, MO-220, QFN-32
ZL30108LDE1	ZARLINK	获取价格	SONET/SDH Network Interface DPLL
ZL30108LDG1	XILINX	获取价格	ATM/SONET/SDH SUPPORT CIRCUIT, QCC32, 5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE,
ZL30108LDG1	MICROCHIP	获取价格	ATM/SONET/SDH Support Circuit, 1-Func