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ZL30106QDG1 PDF预览

ZL30106QDG1

更新时间: 2024-02-23 14:55:10
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 网络接口电信集成电路光电二极管异步传输模式ATM
页数 文件大小 规格书
48页 1048K
描述
SONET/SDH/PDH Network Interface DPLL

ZL30106QDG1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:TFQFP, TQFP64,.47SQ针数:64
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.42JESD-30 代码:S-PQFP-G64
JESD-609代码:e3长度:10 mm
湿度敏感等级:3功能数量:1
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP64,.47SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.8,3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Other Telecom ICs最大压摆率:78 mA
标称供电电压:1.8 V表面贴装:YES
技术:CMOS电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

ZL30106QDG1 数据手册

 浏览型号ZL30106QDG1的Datasheet PDF文件第2页浏览型号ZL30106QDG1的Datasheet PDF文件第3页浏览型号ZL30106QDG1的Datasheet PDF文件第4页浏览型号ZL30106QDG1的Datasheet PDF文件第5页浏览型号ZL30106QDG1的Datasheet PDF文件第6页浏览型号ZL30106QDG1的Datasheet PDF文件第7页 
ZL30106  
SONET/SDH/PDH  
Network Interface DPLL  
Data Sheet  
November 2005  
Features  
Synchronizes to clock-and-sync-pair to maintain  
Ordering Information  
minimal phase skew between inputs and outputs  
ZL30106QDG 64 pin TQFP Trays, Bake & Drypack  
ZL30106QDG1 64 pin TQFP* Trays, Bake & Drypack  
*Pb Free Matte Tin  
Supports output wander and jitter generation  
specifications for SONET/SDH and PDH  
interfaces  
Accepts three input references and synchronizes  
to any combination of 2 kHz, 8 kHz, 1.544 MHz,  
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz  
inputs  
-40°C to +85°C  
Provides lock, holdover and accurate reference  
fail indication  
Selectable loop filter bandwidth of 29 Hz or  
Provides a range of clock outputs:  
922 Hz  
-
2.048 MHz (E1), 16.384 MHz and either  
4.096 MHz and 8.192 MHz or 32.768 MHz and  
65.536 MHz  
Less than 24 psrms intrinsic jitter on the  
19.44 MHz output clock, compliant with GR-253-  
CORE OC-3 and G.813 STM-1 specifications  
-
-
-
19.44 MHz (SONET/SDH)  
Less than 0.6 nspp intrinsic jitter on all PDH output  
clocks and frame pulses  
1.544 MHz (DS1) and 3.088 MHz  
Selectable external master clock source: clock  
oscillator or crystal  
a choice of 6.312 MHz (DS2), 8.448 MHz (E2),  
44.736 MHz (DS3) or 34.368 MHz (E3)  
Simple hardware control interface  
Provides 5 styles of 8 kHz framing pulses and a  
2 kHz multi-frame pulse  
Applications  
Provides automatic entry into Holdover and return  
from Holdover  
Manual and automatic hitless reference switching  
between any combination of valid input reference  
frequencies  
Line card synchronization for SONET/SDH and  
PDH systems  
Wireless base-station Network Interface Card  
AdvancedTCA™ and H.110 line cards  
BW_SEL  
LOCK  
OSCi OSCo TIE_CLR  
OUT_SEL2  
Master Clock  
REF0  
C2o  
REF_SYNC0  
C4/C65o  
C8/C32o  
C16o  
Virtual  
TIE  
Reference  
REF1  
MUX  
Corrector  
Circuit  
REF_SYNC1  
REF2  
E1  
Synthesizer  
DPLL  
F4/F65o  
F8/F32o  
F16o  
C1.5o  
C3o  
C19o  
F2ko  
C6/8.4/34/44o  
OUT_SEL1:0  
REF_FAIL0  
REF_FAIL1  
REF_FAIL2  
APP_SEL1:0  
TIE  
Reference  
Monitor  
DS1  
Corrector  
Enable  
Synthesizer  
SDH  
Synthesizer  
Mode  
Control  
Programmable  
Synthesizer  
REF_SEL1:0  
RST  
State Machine  
Frequency  
Select  
MUX  
IEEE  
TRST  
1149.1a  
HMS  
MODE_SEL1:0  
HOLDOVER  
TCK  
TDO  
TDI TMS  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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