Datasheet > ZL30105_05

ZL30105_05

更新时间： 2024-02-22 09:12:13

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		时钟
页数	文件大小	规格书
52页	1128K
描述
T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110

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ZL30105_05 数据手册

ZL30105

T1/E1/SDH Stratum 3 Redundant System Clock

Synchronizer for AdvancedTCA™ and H.110

Data Sheet

November 2005

Features

•

Synchronizes to clock-and-sync-pair to maintain

Ordering Information

minimal phase skew between the master-clock

and the redundant slave-clock

ZL30105QDG

64 pin TQFP Trays

ZL30105QDG1 64 pin TQFP* Trays Bake & Drypack

* Pb Free Matte Tin

•

Supports ITU-T G.813 option 1, G.823 for

2048 kbit/s and G.824 for 1544 kbit/s interfaces

Supports Telcordia GR-1244-CORE Stratum

-40°C to +85°C

3/4/4E

Supports ANSI T1.403 and ETSI ETS 300 011 for

ISDN primary rate interfaces

Accepts three input references and synchronizes

to any combination of 2 kHz, 8 kHz, 1.544 MHz,

2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz

inputs

Provides a range of clock outputs: 1.544 MHz

(DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz,

and 19.44 MHz (SDH), and either 4.096 MHz and

8.192 MHz or 32.768 MHz and 65.536 MHz, and a

choice of 6.312 MHz (DS2), 8.448 MHz (E2),

44.736 MHz (DS3) or 34.368 MHz (E3)

•

Less than 0.6 ns_ppintrinsic jitter on all output

clocks and frame pulses

Manual or Automatic hitless reference switching

between any combination of valid input reference

frequencies

•

Provides Lock, Holdover and selectable Out of

•

Range indication

•

Simple hardware control interface

Selectable external master clock source: Clock

Oscillator or Crystal

•

Provides 5 styles of 8 kHz framing pulses and a

Applications

2 kHz multi-frame pulse

•

Synchronization and timing control for multi-trunk

SDH and T1/E1 systems such as DSLAMs,

Gateways and PBXs

•

Holdover frequency accuracy of 1x10^-8

Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz

Less than 24 ps_rmsintrinsic jitter on the 19.44 MHz

output clock, compliant with GR-253-CORE OC-3

and G.813 STM-1 specifications

•

Clock and frame pulse source for

AdvancedTCA™- and other time division

multiplex (TDM) buses

FASTLOCK LOCK

OSCi OSCo TIE_CLR

OUT_SEL2

Master Clock

MUX

C2o

C4/C65o

C8/C32o

C16o

Virtual

Reference

REF0

REF1

REF2

TIE

Corrector

Circuit

Synthesizer

DPLL

F4/F65o

F8/F32o

F16o

C1.5o

C3o

C19o

F2ko

C6/8.4/34/44o

OUT_SEL1:0

REF2_SYNC

REF_FAIL0

REF_FAIL1

REF_FAIL2

TIE

Reference

Monitor

DS1

Corrector

Enable

Synthesizer

SDH

Synthesizer

Mode

Control

Programmable

Synthesizer

REF_SEL1:0

RST

State Machine

Frequency

Select

MUX

IEEE

TRST

1149.1a

MODE_SEL1:0

HMS HOLDOVER

SEC_MSTR APP_SEL1:0

TCK TDI TMS TDO

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...52

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与ZL30105_05相关器件

型号	品牌	获取价格	描述	数据表
ZL30105QDG	ZARLINK	获取价格	T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
ZL30105QDG1	ZARLINK	获取价格	T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
ZL30106	ZARLINK	获取价格	SONET/SDH/PDH Network Interface DPLL
ZL30106	MICROCHIP	获取价格	The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which p
ZL30106_05	ZARLINK	获取价格	SONET/SDH/PDH Network Interface DPLL
ZL30106QDG	ZARLINK	获取价格	SONET/SDH/PDH Network Interface DPLL
ZL30106QDG1	ZARLINK	获取价格	SONET/SDH/PDH Network Interface DPLL
ZL30107	ZARLINK	获取价格	GbE Line Card Synchronizer
ZL30107	MICROCHIP	获取价格	The ZL30107 provides timing and synchronization for Ethernet line cards in next-generation
ZL30107GGG	ZARLINK	获取价格	GbE Line Card Synchronizer

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