Datasheet > ZL30102QDG

ZL30102QDG

更新时间： 2024-02-29 12:45:52

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		时钟
页数	文件大小	规格书
50页	479K
描述
T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110

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ZL30102QDG 数据手册

ZL30102

T1/E1 Stratum 4/4E Redundant System

Clock Synchronizer for DS1/E1 and H.110

Data Sheet

October 2004

Features

•

Synchronizes to clock-and-sync-pair to maintain

Ordering Information

minimal phase skew between an H.110 primary

master clock and a secondary master clock

ZL30102QDG

64 pin TQFP

•

Supports Telcordia GR-1244-CORE Stratum 4 and

-40°C to +85°C

Supports ITU-T G.823 and G.824 for 2048 kbit/s

and 1544 kbit/s interfaces

Supports ANSI T1.403 and ETSI ETS 300 011 for

ISDN primary rate interfaces

•

Attenuates wander from 1.8 Hz

Less than 0.6 ns_ppintrinsic jitter on all output

clocks

External master clock source: Clock Oscillator or

Crystal

•

Simple hardware control interface

Manual and Automatic hitless reference switching

•

Accepts three input references and synchronizes

to any combination of 8 kHz, 1.544 MHz,

Applications

•

2.048 MHz, 8.192 MHz or 16.384 MHz inputs

Synchronization and timing control for multi-trunk

DS1/ E1 terminal systems such as DSLAMs,

Gateways and PBXs

•

Provides a range of clock outputs: 1.544 MHz,

2.048 MHz, 3.088 MHz, 6.312 MHz, 16.384 MHz

and either 4.096 MHz and 8.192 MHz or

32.768 MHz and 65.536 MHz

•

Clock and frame pulse source for H.110 CT Bus,

ST-BUS, GCI and other time division multiplex

(TDM) buses

•

Provides 5 styles of 8 kHz framing pulses

Holdover frequency accuracy of 1x10^-7

Provides Lock, Holdover and selectable Out of

Range indication

TIE_CLR

OSCi OSCo

Master Clock

OUT_SEL

FASTLOCK

LOCK

C2o

Virtual

REF0

REF1

REF2

C4/C65o

C8/C32o

C16o

F4/F65o

F8/F32o

F16o

C1.5o

C3o

TIE

Reference

MUX

Corrector

Circuit

DPLL

Synthesizer

REF2_SYNC

Mode

REF_FAIL0

REF_FAIL1

REF_FAIL2

OOR_SEL

Control

TIE

Reference

Monitor

Corrector

Enable

DS1

Synthesizer

DS2

C6o

Synthesizer

REF_SEL1:0

RST

Frequency

Select

State Machine

MUX

IEEE

TRST

1149.1a

MODE_SEL1S:E0C_MSTR

HMS HOLDOVER

TCK TDI TMS TDO

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...50

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与ZL30102QDG相关器件

型号	品牌	获取价格	描述	数据表
ZL30102QDG1	ZARLINK	获取价格	T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
ZL30105	ZARLINK	获取价格	T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
ZL30105	MICROCHIP	获取价格	The ZL30105 is a high-performance DPLL (digital phase-locked loop) designed for synchroniz
ZL30105_05	ZARLINK	获取价格	T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
ZL30105QDG	ZARLINK	获取价格	T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
ZL30105QDG1	ZARLINK	获取价格	T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
ZL30106	ZARLINK	获取价格	SONET/SDH/PDH Network Interface DPLL
ZL30106	MICROCHIP	获取价格	The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which p
ZL30106_05	ZARLINK	获取价格	SONET/SDH/PDH Network Interface DPLL
ZL30106QDG	ZARLINK	获取价格	SONET/SDH/PDH Network Interface DPLL

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