ZL10312QCG

更新时间： 2024-02-21 07:24:42

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		消费电路商用集成电路
页数	文件大小	规格书
15页	332K
描述
Satellite Demodulator

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中文翻译

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技术参数
数据手册

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ZL10312QCG 技术参数

生命周期：	Obsolete	包装说明：	DIE,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	X-XUUC-N20
JESD-609代码：	e0	功能数量：	1
端子数量：	20	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装形状：	UNSPECIFIED
封装形式：	UNCASED CHIP	认证状态：	Not Qualified
最大供电电压 (Vsup)：	1.89 V	最小供电电压 (Vsup)：	1.71 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	NO LEAD
端子位置：	UPPER	Base Number Matches：	1

ZL10312QCG 数据手册

ZL10312

Satellite Demodulator

Data Sheet

November 2004

Features

•

Conforms to EBU specification for DVB-S and

DirecTV specification for DSS

Ordering Information

ZL10312QCG

ZL10312QCF

ZL10312QCG1

ZL10312UBH

64 Pin LQFP

Trays, Bake & Drypack

Tape & Reel

•

On-chip digital filtering supports 1 - 45 MSps

symbol rates

64 Pin LQFP* Trays, Bake & Drypack

Die supplied in wafer form**

•

On-chip 60 or 90 MHz dual-ADC

*Pb Free Matte Tin

**Please contact Sales for further details

High speed scanning mode for blind symbol

rate/code rate acquisition

0°C to +70°C

•

Automatic spectral inversion resolution

Description

High level software interface for minimum

development time

The ZL10312 is

QPSK/BPSK 1 - 45 MSps

demodulator and channel decoder for digital satellite

television transmissions to the European Broadcast

Union ETS 300 421 specification. It receives analogue

I and Q signals from the tuner, digitises and digitally

demodulates this signal, and implements the complete

DVB/DSS FEC (Forward Error Correction), and de-

scrambling function. The output is in the form of

MPEG2 or DSS transport stream data packets. The

ZL10312 also provides automatic gain control to the RF

front-end device.

•

Up to ±22 MHz LNB frequency tracking

DiSEqC™ v2.2: receive/transmit for full control of

LNB, dish and other components

•

Compact 64 pin LQFP package (7 x 7 mm)

Sleep pin gives ~1,000 fold reduction in power to

help products meet ENERGY STAR^®

requirements

Applications

The ZL10312 has a serial 2-wire bus interface to the

control microprocessor. Minimal software is required to

control the ZL10312 because of the built in automatic

search and decode control functions.

•

DVB 1 - 45 MSps compliant satellite receiver

DSS 20 MSps compliant satellite receivers

SMATV trans-modulators. (Single Master

Antenna TV)

•

Satellite PC applications

MPEG/

DSS

I I/P

DVB

DSS

FEC

Packets

Timing recovery

Matched filter

Decimation

Filtering

Dual ADC

De-rotator

Phase recovery

Q I/P

Bus I/O

Analog

AGC

Acquisition

Control

2-Wire Bus

Interface

Clock Generation

Control

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...15

中文翻译

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与ZL10312QCG相关器件

型号	品牌	获取价格	描述	数据表
ZL10312QCG1	ZARLINK	获取价格	Satellite Demodulator
ZL10312UBH	ZARLINK	获取价格	Satellite Demodulator
ZL10313	ZARLINK	获取价格	Satellite Demodulator
ZL10313QCG	ZARLINK	获取价格	Satellite Demodulator
ZL10313QCG1	ZARLINK	获取价格	Satellite Demodulator
ZL10313UBH	ZARLINK	获取价格	Satellite Demodulator
ZL10320	ZARLINK	获取价格	Digital Television PVR-on-a-Chip Processor
ZL10320/GAC	ZARLINK	获取价格	Digital Television PVR-on-a-Chip Processor
ZL10321/GAC	ZARLINK	获取价格	Digital Television PVR-on-a-Chip Processor
ZL10353	ZARLINK	获取价格	Fully Compliant NorDig Unified COFDM Digital Terrestrial TV (DTV) Demodulator

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