ZL10312
Satellite Demodulator
Data Sheet
November 2004
Features
•
Conforms to EBU specification for DVB-S and
DirecTV specification for DSS
Ordering Information
ZL10312QCG
ZL10312QCF
ZL10312QCG1
ZL10312UBH
64 Pin LQFP
64 Pin LQFP
Trays, Bake & Drypack
Tape & Reel
•
On-chip digital filtering supports 1 - 45 MSps
symbol rates
64 Pin LQFP* Trays, Bake & Drypack
Die supplied in wafer form**
•
•
On-chip 60 or 90 MHz dual-ADC
*Pb Free Matte Tin
**Please contact Sales for further details
High speed scanning mode for blind symbol
rate/code rate acquisition
0°C to +70°C
•
•
Automatic spectral inversion resolution
Description
High level software interface for minimum
development time
The ZL10312 is
a
QPSK/BPSK 1 - 45 MSps
demodulator and channel decoder for digital satellite
television transmissions to the European Broadcast
Union ETS 300 421 specification. It receives analogue
I and Q signals from the tuner, digitises and digitally
demodulates this signal, and implements the complete
DVB/DSS FEC (Forward Error Correction), and de-
scrambling function. The output is in the form of
MPEG2 or DSS transport stream data packets. The
ZL10312 also provides automatic gain control to the RF
front-end device.
•
•
Up to ±22 MHz LNB frequency tracking
DiSEqC™ v2.2: receive/transmit for full control of
LNB, dish and other components
•
•
Compact 64 pin LQFP package (7 x 7 mm)
Sleep pin gives ~1,000 fold reduction in power to
help products meet ENERGY STAR®
requirements
Applications
The ZL10312 has a serial 2-wire bus interface to the
control microprocessor. Minimal software is required to
control the ZL10312 because of the built in automatic
search and decode control functions.
•
•
•
DVB 1 - 45 MSps compliant satellite receiver
DSS 20 MSps compliant satellite receivers
SMATV trans-modulators. (Single Master
Antenna TV)
•
Satellite PC applications
MPEG/
DSS
I I/P
DVB
DSS
FEC
Packets
Timing recovery
Matched filter
Decimation
Filtering
Dual ADC
De-rotator
Phase recovery
Q I/P
Bus I/O
Analog
AGC
Acquisition
Control
2-Wire Bus
Interface
Clock Generation
Control
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.