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ZL10311DTV-SOC PDF预览

ZL10311DTV-SOC

更新时间: 2024-02-02 11:07:23
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电视
页数 文件大小 规格书
40页 644K
描述
Digital Television DVB-T-On-a-Chip Processor

ZL10311DTV-SOC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA针数:388
Reach Compliance Code:unknown风险等级:5.92
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PBGA-B388
端子数量:388最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA388,26X26,40
封装形状:SQUARE封装形式:GRID ARRAY
电源:1.8,2.5,3.3 V认证状态:Not Qualified
子类别:Other Consumer ICs表面贴装:YES
温度等级:COMMERCIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM

ZL10311DTV-SOC 数据手册

 浏览型号ZL10311DTV-SOC的Datasheet PDF文件第2页浏览型号ZL10311DTV-SOC的Datasheet PDF文件第3页浏览型号ZL10311DTV-SOC的Datasheet PDF文件第4页浏览型号ZL10311DTV-SOC的Datasheet PDF文件第5页浏览型号ZL10311DTV-SOC的Datasheet PDF文件第6页浏览型号ZL10311DTV-SOC的Datasheet PDF文件第7页 
ZL10310/ZL10311  
Digital Television DVB-T-On-a-Chip  
Processor  
Data Sheet  
Issue 1.0  
November 2002  
Features  
DTV-SoC for Digital Terrestrial Television (DTT)  
Ordering Information  
On-chip DVB-T COFDM demodulator with FEC.  
6 Video DACs on-chip, for Composite or  
ZL10310/GAC  
ZL10311/GAC  
388 ball EPBGA  
388 ball EPBGA  
00C to +700C  
Component (RGB or Y U/V) Analog Video  
Twin PAL/NTSC DENCs  
Low Power (<1.4W Typical)  
Low Component Count  
Unified SDRAM controller  
Smart Card Interface  
I2S Digital Audio Input  
Infrared & UART interface  
I2S and S/PDIF Digital Audio outputs  
MPEG-2 Audio & Video decoders  
DVB-compatible Common Interface (CI) control  
and bitstream interfaces  
PowerPC 405TM CPU Core with 16k/16k cache,  
Memory manager and Virtual memory system  
Multi-stream multiplexing to support internal and  
external demodulators  
External Modem support interface  
Complete Linux-based Software Development Kit  
(SDK)  
Supports MacrovisionTM Copy Protection -  
(ZL10311 only; available to Macrovision license  
holders only)  
IDE interface  
Inputs for external MPEG-2 Transport Streams,  
allowing support for external demodulators (e.g.  
Cable TV, Satellite TV)  
DolbyDigital* Decoding - (ZL10311 only;  
available to DolbyDigital* license holders only -  
*awaiting certification)  
Conditional Access (CA) DVB-descrambler  
Bitstream  
O/P  
Bitstream  
I/P  
/Second  
Smart Card  
Stereo Audio  
DAC  
I2S  
Audio  
ZL10310 / ZL10311 DTV-SOC  
Decoder  
De-mod  
/JTAG  
S/PDIF  
EXTIN  
ADCIN  
JTAG  
Bitstream  
De-  
System  
Multiplexing &  
Control  
scrambler  
DeMultiplex  
Video  
ADC IN  
Decoder  
COFDM  
/De-mod  
DeModulator  
& FEC  
AGC B  
Video Scaler  
/ Blender  
Flash  
IDE  
AUX Bus  
CI Control  
Cached  
R
PowerPC 405  
Sub System  
Comp  
Smart Card  
CODEC/modem  
I2C  
Video  
Video  
DENCs  
/DACs  
Peripherals  
Analog  
Video  
UART/IRDA  
BIT I/O  
8k Boot  
ROM  
SDRAM  
SDRAM  
Y+U/V  
RGB  
Controller  
Controller  
Power Management  
SDRAM 1  
BUS  
SDRAM 0  
BUS  
(optional)  
Figure 1 - Block Diagram of ZL10310 and ZL10311  
1

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