Datasheet > Z8523310ASG

Z8523310ASG

更新时间： 2024-11-04 19:49:19

品牌	Logo	应用领域
IXYS		/
页数	文件大小	规格书
4页	53K
描述
Micro Peripheral IC,

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技术参数
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Z8523310ASG 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.12	Base Number Matches：	1

Z8523310ASG 数据手册

EMSCC™ Enhanced Mono Serial Communication Controller

Z85233

Product Brief

PB005802-0608

•

New Programmable Features Added with

Write Register 7'

FEATURES

•

Hardware and software compatible with

Zilog's SCC/ ESCC™

Write registers: WR3, WR4, WR5, and WR10

are Now Readable

•

Deeper Data FIFOs

•

Read Register 0 Latched During Access

Software Interrupt Acknowledge Mode

–

4-Byte Transmit FIFO

8-Byte Receive FIFO

DPLL Counter Output Available as Jitter-Free

Clock Source

•

Programmable FIFO Interrupt Levels Provide

Flexible Interrupt Response

•

/DTR//REQ Pin Deactivation Time Reduced

Many Improvements toSupport SDLC/

HDLCTransfers:

A Full-Duplex Channel with a Crystal Oscilla-

tor, Baud Rate Generator, and Digital Phase-

Locked Loop.

–

Deactivation of /RTS Pin after Closing

Flag

Automatic Transmission of the Opening

Flag

•

Multi-Protocol Operation Under Program Con-

trol

Automatic Reset of Tx Underrun/EOM

Latch

Asynchronous Mode/Synchronous Mode

–

Complete CRC Reception

GENERAL DESCRIPTION

TxD pin Automatically Forced High with

NRZI Encoding when Using Mark Idle.

The Zilog Enhanced Mono Serial Communication-

Controller, Z85233 EMSCC, is a software compat-

ible CMOS member of the SCC family introduced

by Zilog in 1981. The EMSCC is a full-duplex data

communications controller capable of supporting a

wide range of popular protocols. The Z85233

EMSCC is a single channel version (Channel A) of

Zilog's Z85230 ESCC. Based on Zilog's unique

Superintegration™ Technology, the EMSCC is

compatible with designs using Zilog's SCC and

ESCC to receive and transmit data. It has many

improvements that significantly reduce CPU over-

head. The addition of a 4-byte transmit FIFO and

an 8-byte receive FIFO significantly reduces the

overhead required to provide data to, and get data-

from, the transmitter and receiver.

–

Receive FIFO Automatically Unlocked for

Special Receive Interrupts when Using the

SDLC Status FIFO.

Back-to-Back Frame Transmission Simpli-

fied

•

Easier Interface to Popular CPUs

Fast Speeds:

–

10.0 MHz for Data Rates up to 2.5 Mbit/

Sec.

–

16.384 MHz for Data Rates up to 4.096

Mbit/Sec. -20.0 MHz for Data Rates up to

5.0 Mbit/Sec.

•

Improved SDLC Frame Status FIFO

Low Power CMOS

The EMSCC also has many features that improve

packet handling in SDLC mode. The EMSCC will

www.zilog.com

12 3 4

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与Z8523310ASG相关器件

型号	品牌	获取价格	描述	数据表
Z8523310FSC	ZILOG	获取价格	ZiLOGs Family of Serial Communication Controllers
Z8523310FSC00TR	ZILOG	获取价格	IC ESCC 44QFP
Z8523310FSCXXXX	ZILOG	获取价格	Serial I/O Controller, 0.3125MBps, CMOS, PQFP44, PLASTIC, QFP-44
Z8523310FSG	ZILOG	获取价格	Serial I/O Controller, 1 Channel(s), 0.3125MBps, CMOS, PQFP44, PLASTIC, QFP-44
Z8523310VSC	ZILOG	获取价格	ZiLOGs Family of Serial Communication Controllers
Z8523310VSC00TR	ZILOG	获取价格	IC ESCC 44PLCC
Z8523310VSG	ZILOG	获取价格	EMSCCâ¢ Enhanced Mono Serial Communication C
Z8523316ASG	ZILOG	获取价格	Micro Peripheral IC,
Z8523316FSC	ZILOG	获取价格	ZiLOGs Family of Serial Communication Controllers
Z8523316FSC00TR	ZILOG	获取价格	IC ESCC 44QFP

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