Datasheet > Z8018020FEC

Z8018020FEC

更新时间： 2024-02-01 08:17:16

品牌	Logo	应用领域
ZILOG		微处理器
页数	文件大小	规格书
70页	385K
描述
ENHANCED Z180 MICROPROCESSOR

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Z8018020FEC 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	68
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.69	具有ADC：	NO
地址总线宽度：	19	位大小：	8
最大时钟频率：	20 MHz	DAC 通道：	NO
DMA 通道：	YES	外部数据总线宽度：	8
JESD-30 代码：	S-PQCC-J68	长度：	24.2316 mm
端子数量：	68	最高工作温度：	70 °C
最低工作温度：		PWM 通道：	NO
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	座面最大高度：	4.57 mm
速度：	20 MHz	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	24.2316 mm	uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

Z8018020FEC 数据手册

PRELIMINARY PRODUCT SPECIFICATION

Z80180/Z8S180/

Z8L180 SL1919

ENHANCED Z180 MICROPROCESSOR

FEATURES

■ Code Compatible with Zilog Z80 CPU

■ Two 16-Bit Counter/Timers

■ Extended Instructions

■ Two Enhanced UARTs (up to 512 Kbps)

■ Clock Speeds: 6, 8, 10, 20, 33 MHz

■ Operating Range: 5V (3.3V@ 20 MHz)

■ Two Chain-Linked DMA Channels

■ Low Power-Down Modes

■ On-Chip Interrupt Controllers

■ Three On-Chip Wait-State Generators

■ On-Chip Oscillator/Generator

■ Expanded MMU Addressing (up to 1 MB)

■ Clocked Serial I/O Port

■ Operating Temperature Range: 0 C to +70 C

■ -40 C to +85 C Extended Temperature Range

■ Three Packaging Styles

–

68-Pin PLCC

64-Pin DIP

80-Pin QFP

GENERAL DESCRIPTION

™

The enhanced Z80180/Z8S180/Z8L180 significantly im-

Not only does the Z80180/Z8S180/Z8L180 consume less

power during normal operations than the previous model,

it has also been designed with three modes intended to fur-

proves on the previous Z80180 models while still providing

full backward compatibility with existing Zilog Z80 devices.

The Z80180/Z8S180/Z8L180 now offers faster execution

speeds, power saving modes, and EMI noise reduction.

ther reduce the power consumption. Zilog reduced I pow-

er consumption during STANDBY Mode to a minimum of

10 µA by stopping the external oscillators and internal

clock. The SLEEP mode reduces power by placing the

CPU into a “stopped” state, thereby consuming less cur-

rent while the on-chip I/O device is still operating. The

SYSTEM STOP mode places both the CPU and the on-

chip peripherals into a “stopped” mode, thereby reducing

power consumption even further.

This enhanced Z180 design also incorporates additional

feature enhancements to the ASCIs, DMAs, and I

STANDBY Mode power consumption. With the addition of

“ESCC-like” Baud Rate Generators (BRGs), the two ASCIs

now have the flexibility and capability to transfer data asyn-

chronously at rates of up to 512 Kbps. In addition, the ASCI

receiver has added a 4-byte First In First Out (FIFO) which

can be used to buffer incoming data to reduce the inci-

dence of overrun errors. The DMAs have been modified to

allow for a “chain-linking” of the two DMA channels when

set to take their DMA requests from the same peripherals

device. This feature allows for non-stop DMA operation be-

tween the two DMA channels, reducing the amount of CPU

intervention (Figure 1).

A new clock doubler feature has been implemented in the

Z80180/Z8S180/Z8L180 device that allows the program-

mer to double the internal clock from that of the external

clock. This provides a systems cost savings by allowing

the use of lower cost, lower frequency crystals instead of

the higher cost, and higher speed oscillators.

The Enhanced Z180 is housed in 80-pin QFP, 68-pin

PLCC, and 64-pin DIP packages.

DS971800401

P R E L I M I N A R Y

1-1

12 3 4 5 6 7...70

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