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XRT86VL3X_07

更新时间: 2024-09-26 03:52:59
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艾科嘉 - EXAR /
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153页 2804K
描述
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

XRT86VL3X_07 数据手册

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XRT86VL3x  
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION  
JANUARY 2007  
REV. 1.2.2  
payload content of Receive LAPD Message frames  
from the incoming T1/E1/J1 data stream and write the  
GENERAL DESCRIPTION  
The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s  
DS1/E1/J1 framer and LIU integrated solution  
contents into the Receive HDLC buffers. Each framer  
also contains a Transmit and Overhead Data Input  
port, which permits Data Link Terminal Equipment  
direct access to the outbound T1/E1/J1 frames.  
Likewise, a Receive Overhead output data port  
permits Data Link Terminal Equipment direct access  
to the Data Link bits of the inbound T1/E1/J1 frames.  
3
featuring R technology (Relayless, Reconfigurable,  
Redundancy) that comes in a 2-channel, 4-channel,  
or 8-channel package. The physical interface is  
optimized with internal impedance, and with the  
patented pad structure, the XRT86VL3x provides  
protection from power failures and hot swapping.  
The XRT86VL3x fully meets all of the latest T1/E1/J1  
specifications:  
ANSI T1/E1.107-1988, ANSI T1/  
The XRT86VL3x contains an integrated DS1/E1/J1  
framer and LIU which provide DS1/E1/J1 framing and  
error accumulation in accordance with ANSI/ITU_T  
specifications. Each framer has its own framing  
synchronizer and transmit-receive slip buffers. The  
slip buffers can be independently enabled or disabled  
as required and can be configured to frame to the  
common DS1/E1/J1 signal formats.  
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/  
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and  
ITU G-703, G.704, G706 and G.733, AT&T Pub.  
43801, and ETS 300 011, 300 233, JT G.703, JT  
G.704, JT G706, I.431. Extensive test and diagnostic  
functions include Loop-backs, Boundary scan,  
Pseudo Random bit sequence (PRBS) test pattern  
generation, Performance Monitor, Bit Error Rate  
(BER) meter, forced error insertion, and LAPD  
unchannelized data payload processing according to  
ITU-T standard Q.921.  
Each Framer block contains its own Transmit and  
Receive T1/E1/J1 Framing function. There are 3  
Transmit HDLC controllers per channel which  
encapsulate contents of the Transmit HDLC buffers  
into LAPD Message frames. There are 3 Receive  
HDLC controllers per channel which extract the  
Applications and Features (next page)  
FIGURE 1. XRT86VL3X N-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO  
External Data  
Link Controller  
Local PCM  
Tx Overhead In  
Rx Overhead Out  
Highway  
XRT86VL3x  
1 of N-channels  
1:2 Turns Ratio  
1:1 Turns Ratio  
TTIP  
2-Frame  
Slip Buffer  
Elastic Store  
Tx Serial  
Data In  
Tx LIU  
Interface  
Tx Framer  
Rx Framer  
TRING  
Tx Serial  
Clock  
LLB  
LB  
RTIP  
2-Frame  
Slip Buffer  
Elastic Store  
Rx Serial  
Data Out  
Rx LIU  
Interface  
RRING  
Rx Serial  
Clock  
LIU &  
Loopback  
Control  
PRBS  
Generator &  
Analyser  
HDLC/LAPD  
Controllers  
Performance  
Monitor  
RxLOS  
Line Side  
8kHz sync  
OSC  
DMA  
Interface  
Microprocessor  
Interface  
Signaling &  
Alarms  
JTAG  
Back Plane  
1.544-16.384 Mbit/s  
WR  
ALE_AS  
RD  
4
3
INT  
μP  
A[14:0]  
System (Terminal) Side  
D[7:0]  
Select  
RDY_DTACK  
TxON  
Intel/Motorola µP  
Configuration, Control &  
Status Monitor  
Memory  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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