Datasheet > XQR18V04CC44M

XQR18V04CC44M

更新时间： 2024-09-17 19:36:11

品牌	Logo	应用领域
赛灵思 - XILINX		时钟内存集成电路
页数	文件大小	规格书
16页	161K
描述
Configuration Memory, 512X8, Parallel/serial, CMOS, CQCC44, CERAMIC, LCC-44

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技术参数
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XQR18V04CC44M 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ, LDCC44,.7SQ	针数：	44
Reach Compliance Code：	compliant	ECCN代码：	USML XV(E)
HTS代码：	8542.32.00.71	风险等级：	5.85
最大时钟频率 (fCLK)：	20 MHz	数据保留时间-最小值：	10
耐久性：	2000 Write/Erase Cycles	JESD-30 代码：	S-CQCC-J44
JESD-609代码：	e0	长度：	16.51 mm
内存密度：	4096 bit	内存集成电路类型：	CONFIGURATION MEMORY
内存宽度：	8	功能数量：	1
端子数量：	44	字数：	512 words
字数代码：	512	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	512X8	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QCCJ	封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL/SERIAL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	4.826 mm	最大待机电流：	0.02 A
子类别：	Flash Memories	最大压摆率：	0.05 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	TIN LEAD	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	总剂量：	40k Rad(Si) V
类型：	NOR TYPE	宽度：	16.51 mm
Base Number Matches：	1

XQR18V04CC44M 数据手册

QPro XQR18V04 Radiation

Hardened 4Mbit QML ISP

Configuration Flash PROM

Product Specification

DS082 (v1.5) October 5, 2004

Features

Description

•

Operating Temperature Range: –55°C to +100°C

Xilinx introduces the QPro™ XQR18V04 radiation hard-

ened QML 4Mbit in-system programmable configuration

Flash PROM. The XQR18V04 is a 3.3V latch-up immune,

static SEU immune, rewritable PROM that provides a reli-

able non-volatile method for storing large Xilinx FPGA con-

figuration bitstreams used in space flight systems.

•

Latch-Up Immune to LET >120 MeV/cm²/mg

Guaranteed TID of 30 kRad(Si) per spec 1019.5

Fabricated on Epitaxial Substrate

Low-power advanced CMOS FLASH process memory

cells immune to static single event upset

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after the rising CCLK, data is available on the PROM

DATA (D0) pin that is connected to the FPGA D_INpin. The

FPGA generates the appropriate number of clock pulses to

complete the configuration. When the FPGA is in Slave

Serial mode, the PROM and the FPGA are clocked by an

external clock.

•

Supports SEU Scrubbing for Virtex series FPGAs

In-system programmable 3.3V PROMs for

configuration of Xilinx FPGAs

Endurance of 2,000 program/erase cycles

Program/erase over operational temperature range

•

IEEE Std 1149.1 boundary-scan (JTAG) support

Cascadable for storing longer or multiple bitstreams

Dual configuration modes

When the FPGA is in SelectMAP mode (Slave), an external

oscillator will generate the configuration clock that drives

the PROM and the FPGA. After the rising CCLK edge, data

are available on the PROMs DATA (D0-D7) pins. The data

will be clocked into the FPGA on the following rising edge of

the CCLK. See Figure 3.

Serial Slow/Fast configuration (up to 20 MHz)

Parallel (up to 160 Mbps at 20 MHz)

•

5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals

3.3V or 2.5V output capability

Multiple devices can be cascaded by using the CEO output

to drive the CE input of the following device. The clock

inputs and the DATA outputs of all PROMs in this chain are

interconnected. The XQR18V04 is compatible and can be

cascaded with other configuration PROMs such as the

XQR1701L and XQR17V16 one-time programmable con-

figuration PROMs.

Available in CC44 package

Design support using the Xilinx Alliance Series™ and

Xilinx Foundation Series™ software packages

•

JTAG command initiation of standard FPGA

configuration

OE/Reset

CLK CE

TCK

Data

Control

CEO

Serial

Parallel

Interface

TMS

TDI

and

JTAG

Interface

Memory

D0 DATA

(Serial or Parallel

[Express/SelectMAP] Mode)

Data

Address

TDO

D[1:7]

Express Mode and

SelectMAP Interface

DS026_01_021000

Figure 1: XQR18V04 Series Block Diagram

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS082 (v1.5) October 5, 2004

www.xilinx.com

Product Specification

1-800-255-7778

12 3 4 5 6 7...16

中文翻译

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与XQR18V04CC44M相关器件

型号	品牌	获取价格	描述	数据表
XQR18V04CCG44M	XILINX	获取价格	Configuration Memory, 512X8, Parallel/serial, CMOS, CQCC44, CERAMIC, LCC-44
XQR18V04CCG44V	XILINX	获取价格	Configuration Memory, 512X8, Parallel/serial, CMOS, CQCC44, CERAMIC, LCC-44
XQR18V04VQ44N	XILINX	获取价格	Configuration Memory, CMOS, PQFP44
XQR2V1000-4BG575N	XILINX	获取价格	Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, 11520-Cell, CMOS, PBGA575
XQR2V1000-4BG575R	XILINX	获取价格	Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, 11520-Cell, CMOS, PBGA575
XQR2V1000-4FG456N	XILINX	获取价格	Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, 11520-Cell, CMOS, PBGA456
XQR2V1000-4FGG456N	XILINX	获取价格	Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, CMOS, PBGA456, 1 MM PITCH
XQR2V1000-4FGG456R	XILINX	获取价格	Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, CMOS, PBGA456, 1 MM PITCH
XQR2V3000-4BG728R	XILINX	获取价格	Field Programmable Gate Array, 3584 CLBs, 3000000 Gates, 650MHz, 32256-Cell, CMOS, PBGA728
XQR2V3000-4BGG728N	XILINX	获取价格	Field Programmable Gate Array, 3584 CLBs, 3000000 Gates, 650MHz, CMOS, PBGA728, 1.27 MM PI

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