Datasheet > XG571CTB

XG571CTB

更新时间： 2024-09-23 23:32:55

品牌	Logo	应用领域
其他 - ETC		晶体时钟发生器外围集成电路光电二极管
页数	文件大小	规格书
17页	116K
描述
CPU SYSTEM CLOCK GENERATOR，TSSOP，48PIN，PLASTIC

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中文翻译

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数据手册

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XG571CTB 数据手册

APPROVED PRODUCT

XG571C

SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum

Technology for Pentium® Processor Based Design

Product Features

Frequency Table

SEL

CPU

PCI

30.0

33.3*

•

Supports Pentiumâ and PentiumâPro and Mobil

Pentiumâ Processor designs.

4 CPU clocks up to 8 loads.

Up to 8 SDRAM clocks for 2 DIMMs.

Supports Power Management.

7 PCI synchronous clocks.

Optional common or mixed supply mode:

(Vdd = Vddq3 = Vddq2 = 3.3V) or

(Vdd = Vddq3 = 3.3V, Vddq2 = 2.5V)

< 250ps skew CPU and SDRAM clocks.

< 250ps skew among PCI clocks.

SMBUS 2-Wire serial interface

Programmable registers featuring:

enable/disable each output pin

mode as tri-state, test, or normal

24/48 MHz selections

1 IOAPIC clock for multiprocessor support.

48-pin SSOP and TSSOP package

Spread Spectrum Technology for up to 13dB of

EMI reduction

60.0

•

66.6*

*Spread Spectrum mode capable

Pin Configuration

XG571

REF1

REF0

Vdd

REF2

Vddq2

IOAPIC0

Vss

Xin

Xout

PWR_DWN#

Vss

MODE

Vddq3

CPUCLK0

CPUCLK1

Vddq2

PCICLK_F

PCICLK0

Vss

CPUCLK2

CPUCLK3

Vss

PCICLK1

PCICLK2

PCICLK3

PCICLK4

Vddq3

Block Diagram

Buffers

SDRAM0

SDRAM1

Vddq3

REF0,1,2

IOAPIC0

Xin

REF

OSC

Vddq2

Xout

Buffer

Vddq2

Vddq3

SDATA

SDCLK

PCICLK5

Vss

SDRAM2

SDRAM3

Vss

CPUCLK0~3

Buffers

SEL

SDRAM0~7

PCICLK0~5

Buffers

SEL

PLL1

SDATA

SDCLK

Vddq3

SDRAM4

SDRAM5

Vddq3

dly

Buffers

Buffer

PCI_STOP#

CPU_STOP#

PWR_DWN#

PCICLK_F

MODE

48/24MHZ

Vss

SDRAM6/CPU_STOP#

SDRAM7/PCI_STOP#

Vdd

Buffer

48/24MHZ

PLL2

Cypress Semiconductor Corporation

525 Los Coches St.

Document#: 38-07019 Rev. **

5/17/2001

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

http://www.cypress.com

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