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XCR3128XL-7VQ100C

更新时间： 2024-10-28 22:23:27
品牌 Logo 应用领域
赛灵思 - XILINX /
页数 文件大小 规格书
10页 91K
描述
XCR3128XL 128 Macrocell CPLD

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中文翻译

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XCR3128XL-7VQ100C 数据手册

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XCR3128XL 128 Macrocell CPLD  
0
14  
DS016 (v1.8) January 8, 2002  
Preliminary Product Specification  
Features  
Description  
•
•
•
•
•
Lowest power 128 macrocell CPLD  
The XCR3128XL is a 3.3V 128 macrocell CPLD targeted at  
power sensitive designs that require leading edge program-  
mable logic solutions. A total of eight function blocks provide  
3,000 usable gates. Pin-to-pin propagation delays are  
6.0 ns with a maximum system frequency of 145 MHz.  
6.0 ns pin-to-pin logic delays  
System frequencies up to 145 MHz  
128 macrocells with 3,000 usable gates  
Available in small footprint packages  
-
-
-
144-pin TQFP (108 user I/O pins)  
144-ball CS BGA (108 user I/O)  
100-pin VQFP (84 user I/O)  
TotalCMOS Design Technique for Fast  
Zero Power  
Xilinx offers a TotalCMOS CPLD, both in process technol-  
ogy and design technique. Xilinx employs a cascade of  
CMOS gates to implement its sum of products instead of  
the traditional sense amp approach. This CMOS gate imple-  
mentation allows Xilinx to offer CPLDs that are both high  
performance and low power, breaking the paradigm that to  
have low power, you must have low performance. Refer to  
•
•
Optimized for 3.3V systems  
-
-
-
Ultra low power operation  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
Fast Zero Power™ (FZP) CMOS design  
technology  
-
Figure 1 and Table 1 showing the I vs. Frequency of our  
CC  
XCR3128XL TotalCMOS CPLD (data taken with eight  
resetable up/down, 16-bit counters at 3.3V, 25°C).  
Advanced system features  
-
-
-
-
-
-
-
-
In-system programming  
Input registers  
Predictable timing model  
Up to 23 available clocks per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
70  
60  
50  
40  
Eight product term control terms per function block  
•
•
•
Fast ISP programming times  
30  
20  
10  
Port Enable pin for additional I/O  
2.7V to 3.6V supply voltage at industrial temperature  
range  
•
•
•
Programmable slew rate control per output  
Security bit prevents unauthorized access  
0
Refer to XPLA3 family data sheet (DS012) for  
20  
40  
60  
80  
100 120 140  
0
architecture description  
Frequency (MHz)  
DS016_01_112100  
Figure 1: Typical I vs. Frequency at V = 3.3V, 25°C  
CC  
CC  
Table 1: Typical I vs. Frequency at V = 3.3V, 25°C  
CC  
CC  
Frequency (MHz)  
0
1
5
10  
20  
40  
60  
25.3  
80  
100  
120  
49.7  
140  
Typical I (mA)  
0
0.5  
2.2  
4.4  
8.7  
17.1  
33.6  
41.6  
57.7  
CC  
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS016 (v1.8) January 8, 2002  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
1234567...10

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XCR3128XL-7VQ100C 替代型号

型号 品牌 替代类型 描述 数据表
XCR3128XL-10VQG100C XILINX

完全替代

 EE PLD, 10ns, 128-Cell, CMOS, PQFP100, LEAD FREE, VQFP-100
XCR3128XL-10VQ100C XILINX

完全替代

 XCR3128XL 128 Macrocell CPLD

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XCR3128XL-7VQG100C XILINX

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XCR3256XL-10FT256I XILINX

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XCR3256XL-10FTG256C XILINX

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