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XCR3032XL-5VQ44I PDF预览

XCR3032XL-5VQ44I

更新时间： 2024-11-10 22:12:07
品牌 Logo 应用领域
赛灵思 - XILINX 可编程逻辑器件时钟
页数 文件大小 规格书
8页 85K
描述
XCR3032XL 32 Macrocell CPLD

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中文翻译

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XCR3032XL-5VQ44I 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：QFP
包装说明：TQFP,针数：44
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.14Is Samacsys：N
最大时钟频率：200 MHzJESD-30 代码：S-PQFP-G44
JESD-609代码：e0长度：10 mm
湿度敏感等级：3I/O 线路数量：32
端子数量：44最高工作温度：85 °C
最低工作温度：-40 °C组织：32 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：TQFP封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE峰值回流温度（摄氏度）：225
可编程逻辑类型：EE PLD传播延迟：5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：3.6 V最小供电电压：2.7 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：10 mm
Base Number Matches：1

XCR3032XL-5VQ44I 数据手册

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R
XCR3032XL 32 Macrocell CPLD  
0
14  
DS023 (v1.5) January 8, 2002  
Preliminary Product Specification  
Features  
Description  
•
•
•
•
•
Lowest power 32 macrocell CPLD  
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at  
power sensitive designs that require leading edge program-  
mable logic solutions. A total of two function blocks provide  
750 usable gates. Pin-to-pin propagation delays are 5.0 ns  
with a maximum system frequency of 200 MHz.  
5.0 ns pin-to-pin logic delays  
System frequencies up to 200 MHz  
32 macrocells with 750 usable gates  
Available in small footprint packages  
-
-
-
48-ball CS BGA (36 user I/O pins)  
44-pin VQFP (36 user I/O)  
44-pin PLCC (36 user I/O)  
TotalCMOS Design Technique for Fast  
Zero Power  
Xilinx offers a TotalCMOS CPLD, both in process technol-  
ogy and design technique. Xilinx employs a cascade of  
CMOS gates to implement its sum of products instead of  
the traditional sense amp approach. This CMOS gate imple-  
mentation allows Xilinx to offer CPLDs that are both high  
performance and low power, breaking the paradigm that to  
have low power, you must have low performance. Refer to  
•
•
Optimized for 3.3V systems  
-
-
-
Ultra-low power operation  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
Fast Zero Power™ (FZP) CMOS design  
technology  
-
Figure 1 and Table 1 showing the I vs. Frequency of our  
CC  
XCR3032XL TotalCMOS CPLD (data taken with two  
resetable up/down, 16-bit counters at 3.3V, 25°C).  
Advanced system features  
-
-
-
-
-
-
-
-
In-system programming  
Input registers  
Predictable timing model  
Up to 23 available clocks per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
20  
15  
10  
Eight product term control terms per function block  
•
•
•
Fast ISP programming times  
Port Enable pin for dual function of JTAG ISP pins  
5
0
2.7V to 3.6V supply voltage at industrial temperature  
range  
•
•
•
Programmable slew rate control per macrocell  
Security bit prevents unauthorized access  
0
20  
40  
60  
80 100 120  
140 160 180 200  
Refer to XPLA3 family data sheet (DS012) for  
Frequency (MHz)  
architecture description  
DS023_01_080101  
Figure 1: I vs. Frequency at V = 3.3V, 25°C  
CC  
CC  
Table 1: I vs. Frequency (V = 3.3V, 25°C)  
CC  
CC  
Frequency (MHz)  
0
1
5
10  
20  
50  
100  
200  
20.3  
Typical I (mA)  
0.02  
0.13  
0.54  
1.06  
2.09  
5.2  
10.26  
CC  
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS023 (v1.5) January 8, 2002  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
12345678

中文翻译

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XCR3032XL-7PC44I XILINX

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 		XCR3032XL 32 Macrocell CPLD
XCR3032XL-7PCG44I XILINX

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 		EE PLD, 7.5ns, 32-Cell, CMOS, PQCC44, LEAD FREE, PLASTIC, LCC-44

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