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XCR3032XL-5CS48I

更新时间： 2024-11-10 22:12:07

品牌	Logo	应用领域
赛灵思 - XILINX		/
页数	文件大小	规格书
8页	85K
描述
XCR3032XL 32 Macrocell CPLD

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XCR3032XL-5CS48I 数据手册

XCR3032XL 32 Macrocell CPLD

DS023 (v1.5) January 8, 2002

Preliminary Product Specification

Features

Description

•

Lowest power 32 macrocell CPLD

The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at

power sensitive designs that require leading edge program-

mable logic solutions. A total of two function blocks provide

750 usable gates. Pin-to-pin propagation delays are 5.0 ns

with a maximum system frequency of 200 MHz.

5.0 ns pin-to-pin logic delays

System frequencies up to 200 MHz

32 macrocells with 750 usable gates

Available in small footprint packages

48-ball CS BGA (36 user I/O pins)

44-pin VQFP (36 user I/O)

44-pin PLCC (36 user I/O)

TotalCMOS Design Technique for Fast

Zero Power

Xilinx offers a TotalCMOS CPLD, both in process technol-

ogy and design technique. Xilinx employs a cascade of

CMOS gates to implement its sum of products instead of

the traditional sense amp approach. This CMOS gate imple-

mentation allows Xilinx to offer CPLDs that are both high

performance and low power, breaking the paradigm that to

have low power, you must have low performance. Refer to

•

Optimized for 3.3V systems

Ultra-low power operation

5V tolerant I/O pins with 3.3V core supply

Advanced 0.35 micron five layer metal EEPROM

process

Fast Zero Power™ (FZP) CMOS design

technology

Figure 1 and Table 1 showing the I vs. Frequency of our

XCR3032XL TotalCMOS CPLD (data taken with two

resetable up/down, 16-bit counters at 3.3V, 25°C).

Advanced system features

In-system programming

Input registers

Predictable timing model

Up to 23 available clocks per function block

Excellent pin retention during design changes

Full IEEE Standard 1149.1 boundary-scan (JTAG)

Four global clocks

Eight product term control terms per function block

•

Fast ISP programming times

Port Enable pin for dual function of JTAG ISP pins

2.7V to 3.6V supply voltage at industrial temperature

range

•

Programmable slew rate control per macrocell

Security bit prevents unauthorized access

80 100 120

140 160 180 200

Refer to XPLA3 family data sheet (DS012) for

Frequency (MHz)

architecture description

DS023_01_080101

Figure 1: I vs. Frequency at V = 3.3V, 25°C

Table 1: I vs. Frequency (V = 3.3V, 25°C)

Frequency (MHz)

100

200

20.3

Typical I (mA)

0.02

0.13

0.54

1.06

2.09

5.2

10.26

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS023 (v1.5) January 8, 2002

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

12 3 4 5 6 7 8

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与XCR3032XL-5CS48I相关器件

型号	品牌	获取价格	描述	数据表
XCR3032XL-5CSG48C	XILINX	获取价格	XCR3032XL 32 Macrocell CPLD
XCR3032XL-5CSG48I	XILINX	获取价格	暂无描述
XCR3032XL-5PC44C	XILINX	获取价格	XCR3032XL 32 Macrocell CPLD
XCR3032XL-5PC44I	XILINX	获取价格	XCR3032XL 32 Macrocell CPLD
XCR3032XL-5VQ44C	XILINX	获取价格	XCR3032XL 32 Macrocell CPLD
XCR3032XL-5VQ44I	XILINX	获取价格	XCR3032XL 32 Macrocell CPLD
XCR3032XL-5VQG44C	XILINX	获取价格	XCR3032XL 32 Macrocell CPLD
XCR3032XL-5VQG44I	XILINX	获取价格	EE PLD, 5ns, CMOS, PQFP44, QFP-44
XCR3032XL-7	XILINX	获取价格	XCR3032XL 32 Macrocell CPLD
XCR3032XL-7CS48C	XILINX	获取价格	XCR3032XL 32 Macrocell CPLD

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