5秒后页面跳转
捷配首页

Datasheet > 可编程逻辑 > 可编程逻辑器件> XCR3032XL-5CS48C
XCR3032XL-5CS48C PDF预览

XCR3032XL-5CS48C

更新时间： 2024-11-10 22:12:07
品牌 Logo 应用领域
赛灵思 - XILINX 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
8页 85K
描述
XCR3032XL 32 Macrocell CPLD

阅读下载

中文翻译

获取价格

XCR3032XL-5CS48C 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：FBGA, BGA48,6X8,32针数：48
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：5.13其他特性：YES
最大时钟频率：213 MHz系统内可编程：YES
JESD-30 代码：S-PBGA-B48JESD-609代码：e0
JTAG BST：YES长度：7 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：36宏单元数：32
端子数量：48最高工作温度：70 °C
最低工作温度：组织：0 DEDICATED INPUTS, 36 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：FBGA封装等效代码：BGA48,6X8,32
封装形状：SQUARE封装形式：GRID ARRAY, FINE PITCH
峰值回流温度（摄氏度）：240电源：3.3 V
可编程逻辑类型：EE PLD传播延迟：5 ns
认证状态：Not Qualified座面最大高度：1.8 mm
子类别：Programmable Logic Devices最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：7 mmBase Number Matches：1

XCR3032XL-5CS48C 数据手册

 浏览型号XCR3032XL-5CS48C的Datasheet PDF文件第2页浏览型号XCR3032XL-5CS48C的Datasheet PDF文件第3页浏览型号XCR3032XL-5CS48C的Datasheet PDF文件第4页浏览型号XCR3032XL-5CS48C的Datasheet PDF文件第5页浏览型号XCR3032XL-5CS48C的Datasheet PDF文件第6页浏览型号XCR3032XL-5CS48C的Datasheet PDF文件第7页 
0
R
XCR3032XL 32 Macrocell CPLD  
0
14  
DS023 (v1.5) January 8, 2002  
Preliminary Product Specification  
Features  
Description  
•
•
•
•
•
Lowest power 32 macrocell CPLD  
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at  
power sensitive designs that require leading edge program-  
mable logic solutions. A total of two function blocks provide  
750 usable gates. Pin-to-pin propagation delays are 5.0 ns  
with a maximum system frequency of 200 MHz.  
5.0 ns pin-to-pin logic delays  
System frequencies up to 200 MHz  
32 macrocells with 750 usable gates  
Available in small footprint packages  
-
-
-
48-ball CS BGA (36 user I/O pins)  
44-pin VQFP (36 user I/O)  
44-pin PLCC (36 user I/O)  
TotalCMOS Design Technique for Fast  
Zero Power  
Xilinx offers a TotalCMOS CPLD, both in process technol-  
ogy and design technique. Xilinx employs a cascade of  
CMOS gates to implement its sum of products instead of  
the traditional sense amp approach. This CMOS gate imple-  
mentation allows Xilinx to offer CPLDs that are both high  
performance and low power, breaking the paradigm that to  
have low power, you must have low performance. Refer to  
•
•
Optimized for 3.3V systems  
-
-
-
Ultra-low power operation  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
Fast Zero Power™ (FZP) CMOS design  
technology  
-
Figure 1 and Table 1 showing the I vs. Frequency of our  
CC  
XCR3032XL TotalCMOS CPLD (data taken with two  
resetable up/down, 16-bit counters at 3.3V, 25°C).  
Advanced system features  
-
-
-
-
-
-
-
-
In-system programming  
Input registers  
Predictable timing model  
Up to 23 available clocks per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
20  
15  
10  
Eight product term control terms per function block  
•
•
•
Fast ISP programming times  
Port Enable pin for dual function of JTAG ISP pins  
5
0
2.7V to 3.6V supply voltage at industrial temperature  
range  
•
•
•
Programmable slew rate control per macrocell  
Security bit prevents unauthorized access  
0
20  
40  
60  
80 100 120  
140 160 180 200  
Refer to XPLA3 family data sheet (DS012) for  
Frequency (MHz)  
architecture description  
DS023_01_080101  
Figure 1: I vs. Frequency at V = 3.3V, 25°C  
CC  
CC  
Table 1: I vs. Frequency (V = 3.3V, 25°C)  
CC  
CC  
Frequency (MHz)  
0
1
5
10  
20  
50  
100  
200  
20.3  
Typical I (mA)  
0.02  
0.13  
0.54  
1.06  
2.09  
5.2  
10.26  
CC  
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS023 (v1.5) January 8, 2002  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
12345678

中文翻译

下载PDF

XCR3032XL-5CS48C 替代型号

型号 品牌 替代类型 描述 数据表
XCR3032XL-10CSG48I XILINX

完全替代

 XCR3032XL 32 Macrocell CPLD
XCR3032XL-7CS48C XILINX

完全替代

 XCR3032XL 32 Macrocell CPLD
XCR3032XL-10CS48I XILINX

完全替代

 XCR3032XL 32 Macrocell CPLD

与XCR3032XL-5CS48C相关器件

型号 品牌 获取价格 描述 数据表
XCR3032XL-5CS48I XILINX

获取价格

 		XCR3032XL 32 Macrocell CPLD
XCR3032XL-5CSG48C XILINX

获取价格

 		XCR3032XL 32 Macrocell CPLD
XCR3032XL-5CSG48I XILINX

获取价格

 		暂无描述
XCR3032XL-5PC44C XILINX

获取价格

 		XCR3032XL 32 Macrocell CPLD
XCR3032XL-5PC44I XILINX

获取价格

 		XCR3032XL 32 Macrocell CPLD
XCR3032XL-5VQ44C XILINX

获取价格

 		XCR3032XL 32 Macrocell CPLD
XCR3032XL-5VQ44I XILINX

获取价格

 		XCR3032XL 32 Macrocell CPLD
XCR3032XL-5VQG44C XILINX

获取价格

 		XCR3032XL 32 Macrocell CPLD
XCR3032XL-5VQG44I XILINX

获取价格

 		EE PLD, 5ns, CMOS, PQFP44, QFP-44
XCR3032XL-7 XILINX

获取价格

 		XCR3032XL 32 Macrocell CPLD

与XCR3032XL-5CS48C相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证