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XCR3032XL-10VQG44C PDF预览

XCR3032XL-10VQG44C

更新时间: 2024-11-11 05:54:35
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赛灵思 - XILINX 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
9页 219K
描述
XCR3032XL 32 Macrocell CPLD

XCR3032XL-10VQG44C 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:TQFP, TQFP44,.47SQ,32针数:44
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:12 weeks
风险等级:0.75Is Samacsys:N
其他特性:YES最大时钟频率:95 MHz
系统内可编程:YESJESD-30 代码:S-PQFP-G44
JESD-609代码:e3JTAG BST:YES
长度:10 mm湿度敏感等级:3
专用输入次数:I/O 线路数量:36
宏单元数:32端子数量:44
最高工作温度:70 °C最低工作温度:
组织:0 DEDICATED INPUTS, 36 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:TQFP
封装等效代码:TQFP44,.47SQ,32封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V可编程逻辑类型:EE PLD
传播延迟:10 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Programmable Logic Devices
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

XCR3032XL-10VQG44C 数据手册

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R
XCR3032XL 32 Macrocell CPLD  
0
14  
DS023 (v2.2) September 15, 2008  
Product Specification  
Features  
Description  
Low power 3.3V 32 macrocell CPLD  
4.5 ns pin-to-pin logic delays  
System frequencies up to 213 MHz  
32 macrocells with 750 usable gates  
Available in small footprint packages  
The CoolRunner™ XPLA3 XCR3032XL device is a 3.3V,  
32-macrocell CPLD targeted at power sensitive designs  
that require leading edge programmable logic solutions. A  
total of two function blocks provide 750 usable gates.  
Pin-to-pin propagation delays are as fast as 4.5 ns with a  
maximum system frequency of 213 MHz.  
-
-
48-ball CS BGA (36 user I/O pins)  
44-pin VQFP (36 user I/Os)  
TotalCMOS Design Technique for Fast  
Zero Power  
Optimized for 3.3V systems  
-
-
-
-
Ultra-low power operation  
Typical Standby Current of 17 μA at 25°C  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
CoolRunner XPLA3 CPLDs offer a TotalCMOS solution,  
both in process technology and design technique. Xilinx®  
CPLDs employ a cascade of CMOS gates to implement its  
sum of products instead of the traditional sense amp  
approach. This CMOS gate implementation allows Xilinx to  
offer CPLDs that are both high performance and low power,  
breaking the paradigm that to have low power, one must  
have low performance. Refer to Figure 1 and Table 1 show-  
-
-
Fast Zero Power (FZP) CMOS technology  
3.3V PCI electrical specification compatible  
outputs (no internal clamp diode on any input or  
I/O, no minimum clock input capacitance)  
ing the I vs. Frequency of the XCR3032XL TotalCMOS  
CC  
Advanced system features  
CPLD (data taken with two resetable up/down, 16-bit  
counters at 3.3V, 25° C).  
-
-
-
-
-
-
-
-
In-system programming  
Input registers  
Predictable timing model  
Up to 23 available clocks per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
20  
15  
10  
Eight product term control terms per function block  
Fast ISP programming times  
Port Enable pin for dual function of JTAG ISP pins  
2.7V to 3.6V supply voltage at industrial temperature  
range  
5
0
Programmable slew rate control per macrocell  
Security bit prevents unauthorized access  
Refer to the CoolRunner XPLA3 family data sheet  
0
20  
40  
60  
80 100 120  
140 160 180 200  
(DS012) for architecture description  
Frequency (MHz)  
DS023_01_080101  
Figure 1: I vs. Frequency at V = 3.3V, 25°C  
CC  
CC  
Table 1: I vs. Frequency (V = 3.3V, 25°C)  
CC  
CC  
Frequency (MHz)  
0
1
5
10  
20  
50  
100  
10.26  
200  
Typical I (mA)  
0.017  
0.13  
0.54  
1.06  
2.09  
5.2  
20.3  
CC  
© 2000–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS023 (v2.2) September 15, 2008  
Product Specification  
www.xilinx.com  
1

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