5秒后页面跳转
XCR3032-10VQ44I PDF预览

XCR3032-10VQ44I

更新时间: 2024-11-11 03:14:43
品牌 Logo 应用领域
赛灵思 - XILINX 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
14页 214K
描述
32 Macrocell CPLD

XCR3032-10VQ44I 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP,针数:44
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.66最大时钟频率:58.8 MHz
JESD-30 代码:S-PQFP-G44长度:10 mm
专用输入次数:2I/O 线路数量:32
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C组织:2 DEDICATED INPUTS, 32 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE可编程逻辑类型:EE PLD
传播延迟:12.5 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

XCR3032-10VQ44I 数据手册

 浏览型号XCR3032-10VQ44I的Datasheet PDF文件第2页浏览型号XCR3032-10VQ44I的Datasheet PDF文件第3页浏览型号XCR3032-10VQ44I的Datasheet PDF文件第4页浏览型号XCR3032-10VQ44I的Datasheet PDF文件第5页浏览型号XCR3032-10VQ44I的Datasheet PDF文件第6页浏览型号XCR3032-10VQ44I的Datasheet PDF文件第7页 
This product has been discontinAuedP. PPleaLseICseeAwTwwIO.xiliNnx.cNomO/paTrtinEfo/notify/pdn0007.htm for details.  
0
R
XCR3032: 32 Macrocell CPLD  
0
14*  
DS038 (v1.3) October 9, 2000  
Product Specification  
CMOS process technology and the patented full CMOS  
FZP design technique. For 5V applications, Xilinx also  
offers the high speed XCR5032 CPLD that offers pin-to-pin  
speeds of 6 ns.  
Features  
Industry's first TotalCMOS™ PLD - both CMOS design  
and process technologies  
Fast Zero Power (FZP™) design technique provides  
ultra-low power and very high speed  
High speed pin-to-pin delays of 8ns  
Ultra-low static power of less than 35 µA  
100% routable with 100% utilization while all pins and  
all macrocells are fixed  
The Xilinx FZP CPLDs utilize the patented XPLA  
(eXtended Programmable Logic Array) architecture. The  
XPLA architecture combines the best features of both PLA  
and PAL type structures to deliver high speed and flexible  
logic allocation that results in superior ability to make  
design changes with fixed pinouts. The XPLA structure in  
each logic block provides a fast 8 ns PAL path with five ded-  
icated product terms per output. This PAL path is joined by  
an additional PLA structure that deploys a pool of 32 prod-  
uct terms to a fully programmable OR array that can allo-  
cate the PLA product terms to any output in the logic block.  
This combination allows logic to be allocated efficiently  
throughout the logic block and supports as many as 37  
product terms on an output. The speed with which logic is  
allocated from the PLA array to an output is only 2.5 ns,  
regardless of the number of PLA product terms used, which  
results in worst case tPD's of only 10.5 ns from any pin to  
any other pin. In addition, logic that is common to multiple  
outputs can be placed on a single PLA product term and  
shared across multiple outputs via the OR array, effectively  
increasing design density.  
Deterministic timing model that is extremely simple to  
use  
Two clocks available  
Programmable clock polarity at every macrocell  
Support for asynchronous clocking  
Innovative XPLA™ architecture combines high speed  
with extreme flexibility  
1000 erase/program cycles guaranteed  
20 years data retention guaranteed  
Logic expandable to 37 product terms  
PCI compliant  
Advanced 0.5µ E2CMOS process  
Security bit prevents unauthorized access  
Design entry and verification using industry standard  
and Xilinx CAE tools  
Reprogrammable using industry standard device  
programmers  
Innovative Control Term structure provides either sum  
terms or product terms in each logic block for:  
The XCR3032 CPLDs are supported by industry standard  
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,  
Synopsys, Synario, Viewlogic, and Synplicity), using text  
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-  
ification uses industry standard simulators for functional  
and timing simulation. Development is supported on per-  
sonal computer, Sparc, and HP platforms. Device fitting  
uses a Xilinx developed tool, XPLA Professional (available  
on the Xilinx web site).  
-
-
Programmable 3-state buffer  
Asynchronous macrocell register preset/reset  
Programmable global 3-state pin facilitates ‘bed of nails'  
testing without using logic resources  
Available in both PLCC and VQFP packages  
Description  
The XCR3032 CPLD is reprogrammable using industry  
standard device programmers from vendors such as Data  
I/O, BP Microsystems, SMS, and others.  
The XCR3032 CPLD (Complex Programmable Logic  
Device) is the first in a family of CoolRunner® CPLDs from  
Xilinx. These devices combine high speed and zero power  
in a 32 macrocell CPLD. With the FZP design technique,  
the XCR3032 offers true pin-to-pin speeds of 8 ns, while  
simultaneously delivering power that is less than 35 µA at  
standby without the need for turbo bitsor other power  
down schemes. By replacing conventional sense amplifier  
methods for implementing product terms (a technique that  
has been used in PLDs since the bipolar era) with a cas-  
caded chain of pure CMOS gates, the dynamic power is  
also substantially lower than any competing CPLD. These  
devices are the first TotalCMOS PLDs, as they use both a  
DS038 (v1.3) October 9, 2000  
www.xilinx.com  
1-800-255-7778  
1

与XCR3032-10VQ44I相关器件

型号 品牌 获取价格 描述 数据表
XCR3032-12PC44C XILINX

获取价格

32 Macrocell CPLD
XCR3032-12PC44I XILINX

获取价格

32 Macrocell CPLD
XCR3032-12VQ44C XILINX

获取价格

32 Macrocell CPLD
XCR3032-12VQ44I XILINX

获取价格

32 Macrocell CPLD
XCR3032-8PC44C XILINX

获取价格

32 Macrocell CPLD
XCR3032-8PC44I XILINX

获取价格

32 Macrocell CPLD
XCR3032-8VQ44C XILINX

获取价格

EE PLD, 10.5ns, CMOS, PQFP44, PLASTIC, VQFP-44
XCR3032-8VQ44I XILINX

获取价格

32 Macrocell CPLD
XCR3032XL XILINX

获取价格

XCR3032XL 32 Macrocell CPLD
XCR3032XL-10 XILINX

获取价格

XCR3032XL 32 Macrocell CPLD