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XCKU025-1FFVA1156C PDF预览

XCKU025-1FFVA1156C

更新时间： 2024-01-11 04:16:15
品牌 Logo 应用领域
赛灵思 - XILINX 栅可编程逻辑
页数 文件大小 规格书
46页 1219K
描述
Field Programmable Gate Array,

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XCKU025-1FFVA1156C 技术参数

是否Rohs认证：符合生命周期：Active
包装说明：BGA, BGA1156,34X34,40Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：2.35Is Samacsys：N
JESD-30 代码：S-PBGA-B1156长度：35 mm
可配置逻辑块数量：1152输入次数：312
逻辑单元数量：318150输出次数：312
端子数量：1156最高工作温度：100 °C
最低工作温度：-40 °C组织：1152 CLBS
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA1156,34X34,40封装形状：SQUARE
封装形式：GRID ARRAY包装方法：TRAY
峰值回流温度（摄氏度）：NOT SPECIFIED可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
座面最大高度：3.51 mm最大供电电压：0.979 V
最小供电电压：0.922 V标称供电电压：0.95 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：35 mm
Base Number Matches：1

XCKU025-1FFVA1156C 数据手册

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UltraScale Architecture and  
Product Data Sheet: Overview  
DS890 (v3.6) November 12, 2018  
Product Specification  
General Description  
Xilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of  
system requirements with a focus on lowering total power consumption through numerous innovative technological  
advancements.  
Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and  
next-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation  
transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.  
Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of  
high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power  
options that deliver the optimal balance between the required system performance and the smallest power envelope.  
Virtex® UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI  
technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and  
application requirements through integration of various system-level functions.  
Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory  
available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal  
balance between the required system performance and the smallest power envelope.  
Zynq® UltraScale+ MPSoCs: Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application  
processor with the Arm Cortex-R5 real-time processor and the UltraScale architecture to create the industry's first All  
Programmable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.  
Zynq® UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading  
programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC)  
provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.  
Family Comparisons  
Table 1: Device Resources  
Kintex  
UltraScale  
FPGA  
Kintex  
UltraScale+  
FPGA  
Virtex  
UltraScale  
FPGA  
Virtex  
Zynq  
Zynq  
UltraScale+ UltraScale+ UltraScale+  
FPGA  
MPSoC  
RFSoC  
MPSoC Processing System  
RF-ADC/DAC  
✓
✓
✓
SD-FEC  
✓
System Logic Cells (K)  
Block Memory (Mb)  
UltraRAM (Mb)  
318–1,451  
12.7–75.9  
356–1,143  
12.7–34.6  
0–36  
783–5,541  
44.3–132.9  
862–3,780  
23.6–94.5  
90–360  
0–8  
103–1,143  
4.5–34.6  
0–36  
678–930  
27.8–38.0  
13.5–22.5  
HBM DRAM (GB)  
DSP (Slices)  
768–5,520  
8,180  
1,368–3,528  
6,287  
600–2,880  
4,268  
2,280–12,288  
21,897  
240–3,528  
6,287  
3,145–4,272  
7,613  
DSP Performance (GMAC/s)  
Transceivers  
12–64  
16.3  
16–76  
36–120  
30.5  
32–128  
58.0  
0–72  
8–16  
Max. Transceiver Speed (Gb/s)  
Max. Serial Bandwidth (full duplex) (Gb/s)  
Memory Interface Performance (Mb/s)  
I/O Pins  
32.75  
32.75  
32.75  
2,086  
3,268  
5,616  
8,384  
3,268  
1,048  
2,400  
2,666  
2,400  
2,666  
2,666  
2,666  
312–832  
280–668  
338–1,456  
208–832  
82–668  
280–408  
© Copyright 2013–2018 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are  
trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, Arm1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of Arm in the  
EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.  
DS890 (v3.6) November 12, 2018  
Product Specification  
www.xilinx.com  
1
 
 
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