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XC95144-10PQ100C PDF预览

XC95144-10PQ100C

更新时间: 2024-01-18 07:06:08
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赛灵思 - XILINX 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
9页 76K
描述
XC95144 In-System Programmable CPLD

XC95144-10PQ100C 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:QFP, QFP100,.7X.9针数:100
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.65
Is Samacsys:N其他特性:YES
最大时钟频率:67.7 MHz系统内可编程:YES
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
JTAG BST:YES长度:20 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:81宏单元数:144
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C组织:0 DEDICATED INPUTS, 81 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.7X.9
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):225电源:3.3/5,5 V
可编程逻辑类型:FLASH PLD传播延迟:10 ns
认证状态:Not Qualified座面最大高度:3.4 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

XC95144-10PQ100C 数据手册

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1
XC95144 In-System Programmable  
CPLD  
1
1*  
December 4, 1998 (Version 4.0)  
Product Specification  
Operating current for each design can be approximated for  
specific operating conditions using the following equation:  
Features  
7.5 ns pin-to-pin logic delays on all pins  
to 111 MHz  
I
(mA) =  
CC  
MC  
f
CNT  
(1.7) + MC (0.9) + MC (0.006 mA/MHz) f  
144 macrocells with 3,200 usable gates  
Up to 133 user I/O pins  
5 V in-system programmable  
HP  
Where:  
MC  
LP  
= Macrocells in high-performance mode  
HP  
-
-
Endurance of 10,000 program/erase cycles  
Program/erase over full commercial voltage and  
temperature range  
MC = Macrocells in low-power mode  
LP  
MC = Total number of macrocells used  
f = Clock frequency (MHz)  
Enhanced pin-locking architecture  
Flexible 36V18 Function Block  
-
90 product terms drive any or all of 18 macrocells  
within Function Block  
Global and product term clocks, output enables, set  
and reset signals  
Figure 1 shows a typical calculation for the XC95144  
device.  
-
Extensive IEEE Std 1149.1 boundary-scan (JTAG)  
support  
Programmable power reduction mode in each  
macrocell  
600  
(480)  
Slew rate control on individual outputs  
User programmable ground pin capability  
Extended pattern security features for design protection  
High-drive 24 mA outputs  
400  
High Performance  
Low Power  
(320)  
(300)  
3.3 V or 5 V I/O capability  
200  
Advanced CMOS 5V FastFLASH technology  
Supports parallel programming of more than one  
XC9500 concurrently  
(160)  
Available in 100-pin PQFP, 100-pin TQFP, and 160-pin  
PQFP packages  
0
50  
100  
Clock Frequency (MHz)  
X5898B  
Description  
The XC95144 is a high-performance CPLD providing  
advanced in-system programming and test capabilities for  
general purpose logic integration. It is comprised of eight  
36V18 Function Blocks, providing 3,200 usable gates with  
propagation delays of 7.5 ns. See Figure 2 for the architec-  
ture overview.  
Figure 1: Typical Icc vs. Frequency for XC95144  
Power Management  
Power dissipation can be reduced in the XC95144 by con-  
figuring macrocells to standard or low-power modes of  
operation. Unused macrocells are turned off to minimize  
power dissipation.  
December 4, 1998 (Version 4.0)  
1

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