Datasheet > XC73144

XC73144

更新时间： 2024-11-27 22:12:11

品牌	Logo	应用领域
赛灵思 - XILINX		/
页数	文件大小	规格书
10页	120K
描述
XC7300 CMOS EPLD Family

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XC73144 数据手册

XC7300 CMOS EPLD Family

Product Description

Features

Description

• High-performance Erasable Programmable Logic

Devices (EPLDs)

The XC7300 family employs a unique Dual-Block architec-

ture, which provides high speed operations via Fast Func-

tion Blocks and/or high density capability via High Density

Function Blocks.

– 5 / 7.5 ns pin-to-pin speeds on all fast inputs

– Up to 167 MHz maximum clock frequency

• Advanced Dual-Block architecture

– Fast Function Blocks

Fast Function Blocks (FFBs) provide fast, pin-to-pin

speed and logic throughput for critical decoding and ultra-

fast state machine applications. High-Density Function

Blocks (FBs) provide maximum logic density and system-

level features to implement complex functions with pre-

dictable timing for adders and accumulators, wide func-

tions and state machines requiring large numbers of

product terms, and other forms of complex logic.

– High-Density Function Blocks

(XC7354, XC7372, XC73108, XC73144)

• 100% interconnect matrix

• High-speed arithmetic carry network

– 1 ns ripple-carry delay per bit

– 43 to 61 MHz 18-bit accumulators

In addition, the XC7300 architecture employs the Univer-

sal Interconnect Matrix (UIM) which guarantees 100%

interconnect of all internal functions. This interconnect

scheme provides constant, short interconnect delays for

all routing paths through the UIM. Constant interconnect

delays simplify device timing and guarantee design perfor-

mance, regardless of logic placement within the chip.

• Multiple independent clocks

• Each input programmable as direct, latched, or

registered

• High-drive 24 mA output

• I/O operation at 3.3 V or 5 V

All XC7300 devices are designed in 0.8µ CMOS EPROM

technology.

• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V

• Power management options

All XC7300 EPLDs include programmable power manage-

ment features to specify high-performance or low-power

operation on an individual Macrocell-by-Macrocell basis.

Unused Macrocells are automatically turned off to mini-

• Multiple security bits for design protection

• Supported by industry standard design and verification

tools

• 100% PCI compliant

The XC7300 Family

XC7318

XC7336

XC7354

XC7372

XC73108

XC73144

Typical 22V10 Equivalent

Number of Macrocells

Number of Function Blocks

Number of Flip-Flops

1.5 – 2

3 – 4

108

144

108

126

198

276

Number of Fast Inputs

Number of Signal Pins

120

156

2-1

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与XC73144相关器件

型号	品牌	获取价格	描述	数据表
XC73144-10	XILINX	获取价格	144-Macrocell CMOS EPLD
XC73144-10BG225C	XILINX	获取价格	OT PLD, 22ns, 144-Cell, CMOS, PBGA225, PLASTIC, BGA-225
XC73144-10PG184M	XILINX	获取价格	UV PLD, CMOS, CPGA184, CERAMIC, PGA-184
XC73144-10WB225C	ETC	获取价格	UV-Erasable/OTP Complex PLD
XC73144-12	XILINX	获取价格	144-Macrocell CMOS EPLD
XC73144-12BG225C	XILINX	获取价格	OT PLD, 30ns, 144-Cell, CMOS, PBGA225, PLASTIC, BGA-225
XC73144-12BG225I	XILINX	获取价格	OT PLD, 30ns, 144-Cell, CMOS, PBGA225, PLASTIC, BGA-225
XC73144-12PG184C	XILINX	获取价格	UV PLD, 30ns, CMOS, CPGA184, WINDOWED, CERAMIC, PGA-184
XC73144-12PG184I	XILINX	获取价格	UV PLD, 30ns, CMOS, CPGA184, WINDOWED, CERAMIC, PGA-184
XC73144-12PG184M	XILINX	获取价格	UV PLD, CMOS, CPGA184,

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