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XC73144-7PQ160C

更新时间： 2024-11-27 22:12:11

品牌	Logo	应用领域
赛灵思 - XILINX		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
11页	113K
描述
144-Macrocell CMOS EPLD

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XC73144-7PQ160C 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	PLASTIC, QFP-160
针数：	160	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.89
其他特性：	144 MACROCELLS; CONFIGURABLE I/O OPERATION-3.3V OR 5V; 3 EXTERNAL CLOCKS; 276 FLIP-FLOPS	最大时钟频率：	83.3 MHz
系统内可编程：	NO	JESD-30 代码：	S-PQFP-G160
JESD-609代码：	e0	JTAG BST：	NO
长度：	28 mm	湿度敏感等级：	3
专用输入次数：	12	I/O 线路数量：	110
宏单元数：	144	端子数量：	160
最高工作温度：	70 °C	最低工作温度：
组织：	12 DEDICATED INPUTS, 110 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP160,1.2SQ	封装形状：	SQUARE
封装形式：	FLATPACK	电源：	3.3/5,5 V
可编程逻辑类型：	OT PLD	传播延迟：	18 ns
认证状态：	Not Qualified	座面最大高度：	4.1 mm
子类别：	Programmable Logic Devices	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	28 mm
Base Number Matches：	1

XC73144-7PQ160C 数据手册

XC73144

144-Macrocell CMOS EPLD

Product Speciﬁcations

The Universal Interconnect Matrix connects the Function

Blocks to each other and to all input pins, providing 100%

connectivity between the Function Blocks. This allows

logic functions to be mapped into the Function Blocks and

interconnected without routing restrictions.

Features

• High-Performance EPLD

– 7.5 ns pin-to-pin speed on all fast inputs

– 100 MHz maximum clock frequency

• Advanced Dual-Block architecture

– Four Fast Function Blocks

The XC73144 is designed in a 0.8 µ CMOS EPROM tech-

nology.

– Twelve High-Density Function Blocks

In addition, the XC73144 includes a programmable power

management feature to specify high-performance or low-

power operation on an individual Macrocell-by-Macrocell

basis. Unused Macrocells are automatically turned off to

minimize power dissipation. Designers can operate

speed-critical paths at maximum performance, while non-

critical paths dissipate less power.

• 100% interconnect matrix

• High-Speed arithmetic carry network

– 1 ns ripple-carry delay per bit

– 43 MHz 16-bit accumulators

• 144 Macrocells with programmable I/O architecture

• Up to 132 inputs programmable as direct, latched, or

registered

Xilinx development software (XEPLD) supports all mem-

bers of XC7300 family. The designer can create, imple-

ment, and verify digital logic circuits for EPLD devices

using the Xilinx XEPLD Development System. Designs

can be represented as schematics consisting of XEPLD

library components, as behavioral descriptions, or as a

mixture of both. The XEPLD translator automatically per-

forms logic optimization, collapsing, mapping and routing

without user intervention. After compiling the design,

XEPLD translator produces documentation for design

analysis and creates a programming ﬁle to conﬁgure the

device.

• All outputs with 24 mA drive

• 3.3 V or 5 V I/O operation

• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V

• Power management options

• Multiple security bits for design protection

• 160-pin plastic quad flat pack and 225-pin ball-grid-

array packages

• 100% PCI compliant

The following lists some of the XEPLD Development Sys-

tem features.

• Programmable slew rate

• Programmable ground control

• Familiar design approach similar to TTL and PLD

techniques

General Description

• Converts netlist to fuse map in minutes using a 386/

486 PC or workstation platform

The XC73144 is a member of the Xilinx Dual-Block EPLD

family. It consists of four Fast Function Blocks and twelve

High-Density Function Blocks interconnected by a central

Universal Interconnect Matrix (UIM).

• Interfaces to standard third-party CAE schematics,

simulation tools, and behavioral languages

• Timing simulation using Viewsim, OrCAD VST, Mentor,

LMC and other tools compatible with the Xilinx Netlist

Format (XNF)

The sixteen Function Blocks in the XC73144 are PAL-like

structures, complete with programmable product term

arrays and programmable multilevel Macrocells. Each

Function Block receives 24 inputs, contains nine Macro-

cells conﬁgurable for registered or combinatorial logic and

produces nine outputs which feedback to the UIM and

output pins.

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与XC73144-7PQ160C相关器件

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XC73144-7WB225C	ETC	获取价格	UV-Erasable/OTP Complex PLD
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XC7318-5PQ44C	XILINX	获取价格	OT PLD, 8.5ns, 18-Cell, CMOS, PQFP44, PLASTIC, QFP-44
XC7318-7PC44C	XILINX	获取价格	OT PLD, 12ns, 18-Cell, CMOS, PQCC44, PLASTIC, LCC-44
XC7336	XILINX	获取价格	XC7300 CMOS EPLD Family
XC7336-10	XILINX	获取价格	36-Macrocell CMOS EPLD
XC7336-10PC44I	XILINX	获取价格	OT PLD, 15ns, 36-Cell, CMOS, PQCC44, PLASTIC, LCC-44
XC7336-10PQ44C	XILINX	获取价格	OT PLD, 15ns, 36-Cell, CMOS, PQFP44, PLASTIC, QFP-44
XC7336-10WC44C	XILINX	获取价格	UV PLD, 15ns, 36-Cell, CMOS, CQCC44, WINDOWED, CERAMIC, LCC-44
XC7336-10WC44I	XILINX	获取价格	UV PLD, 15ns, 36-Cell, CMOS, CQCC44, WINDOWED, CERAMIC, LCC-44

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