`
0
R
Virtex-4 Family Overview
0
0
DS112 (v2.0) January 23, 2007
Preliminary Product Specification
General Description
Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex™-4
Family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC
technology. Virtex-4 FPGAs comprise three platform families—LX, FX, and SX—offering multiple feature choices and
combinations to address all complex applications. The wide array of Virtex-4 hard-IP core blocks includes the PowerPC™
processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP
slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex- 4 building blocks
are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families,
so previous-generation designs are upward compatible. Virtex-4 devices are produced on a state-of-the-art 90-nm copper
process using 300-mm (12-inch) wafer technology..
Summary of Virtex-4 Family Features
•
Three Families — LX/SX/FX
•
SelectIO™ Technology
-
-
Virtex-4 LX: High-performance logic applications solution
Virtex-4 SX: High-performance solution for digital signal
processing (DSP) applications
Virtex-4 FX: High-performance, full-featured solution for
embedded platform applications
-
-
-
-
1.5V to 3.3V I/O operation
Built-in ChipSync™ source-synchronous technology
Digitally controlled impedance (DCI) active termination
Fine grained I/O banking (configuration in one bank)
-
•
•
•
•
•
Flexible Logic Resources
•
•
•
Xesium™ Clock Technology
Secure Chip AES Bitstream Encryption
90-nm Copper CMOS Process
1.2V Core Voltage
Flip-Chip Packaging including Pb-Free Package
Choices
-
-
-
Digital clock manager (DCM) blocks
Additional phase-matched clock dividers (PMCD)
Differential global clocks
XtremeDSP™ Slice
-
-
-
18 x 18, two’s complement, signed Multiplier
Optional pipeline stages
Built-in Accumulator (48-bit) and Adder/Subtracter
•
•
RocketIO™ 622 Mb/s to 6.5 Gb/s Multi-Gigabit
Transceiver (MGT) [FX only]
IBM PowerPC RISC Processor Core [FX only]
Smart RAM Memory Hierarchy
-
Distributed RAM
-
Dual-port 18-Kbit RAM blocks
-
-
PowerPC 405 (PPC405) Core
Auxiliary Processor Unit Interface (User Coprocessor)
·
·
Optional pipeline stages
Optional programmable FIFO logic automatically
remaps RAM signals as FIFO signals
•
Multiple Tri-Mode Ethernet MACs [FX only]
-
High-speed memory interface supports DDR and DDR-2
SDRAM, QDR-II, and RLDRAM-II.
Table 1: Virtex-4 FPGA Family Members
(1)
Block RAM
Max
Configurable Logic Blocks (CLBs)
Max
PowerPC
Processor Ethernet Transceiver
RocketIO
Total Max
I/O User
Banks I/O
(3)
Array
Logic
Cells
Distributed XtremeDSP 18 Kb
Slices RAM (Kb)
Block
Slices(2) Blocks RAM (Kb)
Blocks
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MACs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Blocks
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Device
DCMs PMCDs
Row x Col
32
48
64
64
80
96
96
96
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
64 x 24
96 x 28
13,824 6,144
24,192 10,752
96
168
288
416
560
768
1056
1392
48
72
864
4
8
0
4
4
4
8
8
8
8
9
320
448
640
640
768
960
960
960
1,296
1,728
2,880
3,600
4,320
5,184
6,048
11
13
13
15
17
17
17
128 x 36 41,472 18,432
128 x 52 59,904 26,624
160 x 56 80,640 35,840
96
8
160
200
240
288
336
8
12
12
12
12
XC4VLX100 192 x 64 110,592 49,152
XC4VLX160 192 x 88 152,064 67,584
XC4VLX200 192 x 116 200,448 89,088
© 2004–2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS112 (v2.0) January 23, 2007
www.xilinx.com
Preliminary Product Specification
1