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XC4000E and XC4000X Series Field
Programmable Gate Arrays
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May 14, 1999 (Version 1.6)
Product Specification
XC4000E and XC4000X Series
Features
Low-Voltage Versions Available
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Low-Voltage Devices Function at 3.0 - 3.6 Volts
XC4000XL: High Performance Low-Voltage Versions of
XC4000EX devices
Note: Information in this data sheet covers the XC4000E,
XC4000EX, and XC4000XL families. A separate data sheet
covers the XC4000XLA and XC4000XV families. Electrical
Specifications and package/pin information are covered in
separate sections for each family to make the information
easier to access, review, and print. For access to these sec-
tions, see the Xilinx WEBLINX web site at
Additional XC4000X Series Features
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Highest Performance — 3.3 V XC4000XL
Highest Capacity — Over 180,000 Usable Gates
5 V tolerant I/Os on XC4000XL
0.35 µm SRAM process for XC4000XL
Additional Routing Over XC4000E
http://www.xilinx.com/partinfo/databook.htm#xc4000.
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System featured Field-Programmable Gate Arrays
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almost twice the routing capacity for high-density
designs
Select-RAMTM memory: on-chip ultra-fast RAM with
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synchronous write option
dual-port RAM option
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Buffered Interconnect for Maximum Speed Blocks
Improved VersaRingTM I/O Interconnect for Better Fixed
Pinout Flexibility
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Fully PCI compliant (speed grades -2 and faster)
Abundant flip-flops
Flexible function generators
Dedicated high-speed carry logic
Wide edge decoders on each edge
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
networks
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12 mA Sink Current Per XC4000X Output
Flexible New High-Speed Clock Network
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Eight additional Early Buffers for shorter clock delays
Virtually unlimited number of clock signals
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Optional Multiplexer or 2-input Function Generator on
Device Outputs
Four Additional Address Bits in Master Parallel
Configuration Mode
XC4000XV Family offers the highest density with
0.25 µm 2.5 V technology
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System Performance beyond 80 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
Introduction
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IEEE 1149.1-compatible boundary scan logic
support
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
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Individually programmable output slew rate
Programmable input pull-up or pull-down resistors
12 mA sink current per XC4000E output
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Configured by Loading Binary File
Unlimited re-programmability
Read Back Capability
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The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
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Program verification
Internal node observability
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Backward Compatible with XC4000 Devices
Development System runs on most common computer
platforms
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Interfaces to popular design environments
Fully automatic mapping, placement and routing
Interactive design editor for design optimization
The XC4000E and XC4000X Series currently have 20
members, as shown in Table 1.
May 14, 1999 (Version 1.6)
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