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XC3S50AN-5FG400C

更新时间： 2024-11-09 06:23:35
品牌 Logo 应用领域
赛灵思 - XILINX 栅
页数 文件大小 规格书
112页 3270K
描述
Field Programmable Gate Array, 176 CLBs, 50000 Gates, 770MHz, CMOS, PBGA400, FBGA-400

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XC3S50AN-5FG400C 数据手册

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Spartan-3AN FPGA Family  
Data Sheet  
0
0
DS557 November 19, 2009  
Product Specification  
-
-
Bitstream Sizes  
Detailed Descriptions by Mode  
Module 1: Introduction and Ordering  
Information  
DS557-1 (v3.2) November 19, 2009  
·
·
·
·
·
·
·
Self-contained In-System Flash mode  
Master Serial Mode using Platform Flash PROM  
Master SPI Mode using Commodity Serial Flash  
Master BPI Mode using Commodity Parallel Flash  
Slave Parallel (SelectMAP) using a Processor  
Slave Serial using a Processor  
•
•
•
•
•
•
•
•
Introduction  
Features  
Architectural Overview  
Configuration Overview  
In-system Flash Memory Overview  
General I/O Capabilities  
Supported Packages and Package Marking  
Ordering Information  
JTAG Mode  
-
-
-
ISE iMPACT Programming Examples  
MultiBoot Reconfiguration  
Design Authentication using Device DNA  
•
•
UG333: Spartan-3AN In-System Flash User Guide  
UG334: Spartan-3AN Starter Kit User Guide  
Module 2: Functional Description  
DS557-2 (v3.2) November 19, 2009  
Module 3: DC and Switching Characteristics  
The functionality of the Spartan®-3AN FPGA family is  
described in the following documents:  
DS557-3 (v3.2) November 19, 2009  
•
DC Electrical Characteristics  
•
UG331: Spartan-3 Generation FPGA User Guide  
-
-
-
Absolute Maximum Ratings  
Supply Voltage Specifications  
Recommended Operating Conditions  
-
-
-
-
Clocking Resources  
Digital Clock Managers (DCMs)  
Block RAM  
•
Switching Characteristics  
Configurable Logic Blocks (CLBs)  
-
-
-
-
-
-
-
-
I/O Timing  
Configurable Logic Block (CLB) Timing  
Multiplier Timing  
·
·
·
Distributed RAM  
SRL16 Shift Registers  
Carry and Arithmetic Logic  
Block RAM Timing  
-
-
-
-
-
-
-
-
-
I/O Resources  
Digital Clock Manager (DCM) Timing  
Suspend Mode Timing  
Device DNA Timing  
Embedded Multiplier Blocks  
Programmable Interconnect  
ISE® Design Tools and IP Cores  
Embedded Processing and Control Solutions  
Pin Types and Package Overview  
Package Drawings  
Configuration and JTAG Timing  
Module 4: Pinout Descriptions  
DS557-4 (v3.2) November 19, 2009  
Powering FPGAs  
Power Management  
•
•
•
•
Pin Descriptions  
Package Overview  
Pinout Tables  
•
UG332: Spartan-3 Generation Configuration User Guide  
-
-
Configuration Overview  
Configuration Pins and Behavior  
Footprint Diagrams  
Table 1: Production Status of Spartan-3AN FPGAs  
Spartan-3AN FPGA  
XC3S50AN  
Status  
Production  
Production  
Production  
Production  
Production  
XC3S200AN  
XC3S400AN  
XC3S700AN  
XC3S1400AN  
Additional information on the Spartan-3AN family can be found at http://www.xilinx.com/products/spartan3a/3an.htm.  
© Copyright 2007–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and  
other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.  
DS557 November 19, 2009  
www.xilinx.com  
Product Specification  
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XC3S700A-4FGG400C XILINX

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 		Field Programmable Gate Array, 1472 CLBs, 700000 Gates, 250MHz, 13248-Cell, CMOS, PBGA400,
XC3S700A-4FGG400I XILINX

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 		Field Programmable Gate Array, 1472 CLBs, 700000 Gates, 250MHz, 13248-Cell, CMOS, PBGA400,
XC3S700A-4FGG484C XILINX

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 		Field Programmable Gate Array, 1472 CLBs, 700000 Gates, 250MHz, 13248-Cell, CMOS, PBGA484,

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