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XC3S50A

更新时间： 2024-11-08 07:07:55
品牌 Logo 应用领域
赛灵思 - XILINX /
页数 文件大小 规格书
132页 5929K
描述
Very low cost, high-performance logic solution for high-volume, cost-conscious applications

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XC3S50A 数据手册

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Spartan-3A FPGA Family:  
Data Sheet  
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DS529 August 19, 2010  
Product Specification  
Module 1:  
Introduction and Ordering Information  
Module 3:  
DC and Switching Characteristics  
DS529-1 (v2.0) August 19, 2010  
DS529-3 (v2.0) August 19, 2010  
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Introduction  
Features  
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DC Electrical Characteristics  
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Absolute Maximum Ratings  
Supply Voltage Specifications  
Recommended Operating Conditions  
Architectural and Configuration Overview  
General I/O Capabilities  
Production Status  
Supported Packages and Package Marking  
Ordering Information  
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Switching Characteristics  
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I/O Timing  
Configurable Logic Block (CLB) Timing  
Multiplier Timing  
Block RAM Timing  
Module 2:  
Digital Clock Manager (DCM) Timing  
Suspend Mode Timing  
Device DNA Timing  
Spartan-3A FPGA Family: Functional  
Description  
Configuration and JTAG Timing  
DS529-2 (v2.0) August 19, 2010  
The functionality of the Spartan®-3A FPGA family is  
described in the following documents.  
Module 4:  
Pinout Descriptions  
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UG331: Spartan-3 Generation FPGA User Guide  
DS529-4 (v2.0) August 19, 2010  
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Clocking Resources  
Digital Clock Managers (DCMs)  
Block RAM  
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Pin Descriptions  
Package Overview  
Pinout Tables  
Configurable Logic Blocks (CLBs)  
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Distributed RAM  
SRL16 Shift Registers  
Carry and Arithmetic Logic  
Footprint Diagrams  
For more information on the Spartan-3A FPGA family, go to  
www.xilinx.com/spartan3a  
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I/O Resources  
Embedded Multiplier Blocks  
Programmable Interconnect  
ISE® Design Tools and IP Cores  
Embedded Processing and Control Solutions  
Pin Types and Package Overview  
Package Drawings  
Spartan-3A FPGA  
XC3S50A  
Status  
Production  
Production  
Production  
Production  
Production  
Powering FPGAs  
Power Management  
XC3S200A  
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UG332: Spartan-3 Generation Configuration User Guide  
XC3S400A  
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Configuration Overview  
Configuration Pins and Behavior  
Bitstream Sizes  
XC3S700A  
XC3S1400A  
Detailed Descriptions by Mode  
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Master Serial Mode using Platform Flash PROM  
Master SPI Mode using Commodity Serial Flash  
Master BPI Mode using Commodity Parallel Flash  
Slave Parallel (SelectMAP) using a Processor  
Slave Serial using a Processor  
JTAG Mode  
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ISE iMPACT Programming Examples  
MultiBoot Reconfiguration  
Design Authentication using Device DNA  
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UG334: Spartan-3A/3AN FPGA Starter Kit User Guide  
© Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and  
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.  
DS529 August 19, 2010  
www.xilinx.com  
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Product Specification  
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与XC3S50A相关器件

型号 品牌 获取价格 描述 数据表
XC3S50A-4FTG256C XILINX

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 		Field Programmable Gate Array, 176 CLBs, 50000 Gates, 250MHz, 1584-Cell, CMOS, PBGA256, LE
XC3S50A-4TQG144C XILINX

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 		Field Programmable Gate Array, 176 CLBs, 50000 Gates, 250MHz, 1584-Cell, CMOS, PQFP144, LE
XC3S50A-4TQG144I XILINX

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 		Field Programmable Gate Array, 176 CLBs, 50000 Gates, 250MHz, 1584-Cell, CMOS, PQFP144, LE
XC3S50A-4VQG100C XILINX

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 		Field Programmable Gate Array, 176 CLBs, 50000 Gates, 667MHz, 1584-Cell, CMOS, PQFP100, 16
XC3S50A-5FTG256C XILINX

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 		Field Programmable Gate Array, 176 CLBs, 50000 Gates, 280MHz, 1584-Cell, CMOS, PBGA256, LE
XC3S50AN-4FG484C XILINX

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 		Field Programmable Gate Array, 176 CLBs, 50000 Gates, 667MHz, CMOS, PBGA484, FBGA-484
XC3S50AN-4FGG400C XILINX

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 		Field Programmable Gate Array, 176 CLBs, 50000 Gates, 667MHz, CMOS, PBGA400, ROHS COMPLIAN
XC3S50AN-4FGG484C XILINX

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 		Field Programmable Gate Array, 176 CLBs, 50000 Gates, 667MHz, CMOS, PBGA484, ROHS COMPLIAN
XC3S50AN-4FGG484I XILINX

获取价格

 		Field Programmable Gate Array, 176 CLBs, 50000 Gates, 667MHz, CMOS, PBGA484, ROHS COMPLIAN
XC3S50AN-4TQG144C XILINX

获取价格

 		Field Programmable Gate Array, 176 CLBs, 50000 Gates, 280MHz, 1584-Cell, CMOS, PQFP144, 20

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