Product Obsolete or Under Obsolescence
0
XC3000 Series
R
Field Programmable Gate Arrays
(XC3000A/L, XC3100A/L)
0
7*
November 9, 1998 (Version 3.1)
Product Description
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Complete Development System
Features
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Schematic capture, automatic place and route
Logic and timing simulation
Interactive design editor for design optimization
Timing calculator
Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others
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Complete line of four related Field Programmable Gate
Array product families
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XC3000A, XC3000L, XC3100A, XC3100L
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Ideal for a wide range of custom VLSI design tasks
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Replaces TTL, MSI, and other PLD logic
Integrates complete sub-systems into a single
package
Additional XC3100A Features
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Avoids the NRE, time delay, and risk of conventional
masked gate arrays
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Ultra-high-speed FPGA family with six members
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50-85 MHz system clock rates
190 to 370 MHz guaranteed flip-flop toggle rates
1.55 to 4.1 ns logic delays
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High-performance CMOS static memory technology
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Guaranteed toggle rates of 70 to 370 MHz, logic
delays from 7 to 1.5 ns
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High-end additional family member in the 22 X 22 CLB
array-size XC3195A device
8 mA output sink current and 8 mA source current
Maximum power-down and quiescent current is 5 mA
100% architecture and pin-out compatible with other
XC3000 families
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System clock speeds over 85 MHz
Low quiescent and active power consumption
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Flexible FPGA architecture
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Compatible arrays ranging from 1,000 to 7,500 gate
complexity
Extensive register, combinatorial, and I/O
capabilities
7
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Software and bitstream compatible with the XC3000,
XC3000A, and XC3000L families
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High fan-out signal distribution, low-skew clock nets
Internal 3-state bus capabilities
TTL or CMOS input thresholds
On-chip crystal oscillator amplifier
XC3100A combines the features of the XC3000A and
XC3100 families:
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Additional interconnect resources for TBUFs and CE
inputs
Error checking of the configuration bitstream
Soft startup holds all outputs slew-rate limited during
initial power-up
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Unlimited reprogrammability
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Easy design iteration
In-system logic changes
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Extensive packaging options
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Over 20 different packages
Plastic and ceramic surface-mount and pin-grid-
array packages
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More advanced CMOS process
Low-Voltage Versions Available
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Thin and Very Thin Quad Flat Pack (TQFP and
VQFP) options
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Low-voltage devices function at 3.0 - 3.6 V
XC3000L - Low-voltage versions of XC3000A devices
XC3100L - Low-voltage versions of XC3100A devices
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Ready for volume production
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Standard, off-the-shelf product availability
100% factory pre-tested devices
Excellent reliability record
Max Logic Typical Gate
User I/Os
Max
Horizontal Configuration
Device
CLBs Array
64 8 x 8
Flip-Flops
Gates
1,500
2,000
3,000
4,500
6,000
7,500
Range
Longlines
Data Bits
14,779
22,176
30,784
46,064
64,160
94,984
XC3020A, 3020L, 3120A
XC3030A, 3030L, 3130A
XC3042A, 3042L, 3142A, 3142L
XC3064A, 3064L, 3164A
XC3090A, 3090L, 3190A, 3190L
XC3195A
1,000 - 1,500
64
80
256
360
16
20
24
32
40
44
1,500 - 2,000 100 10 x 10
2,000 - 3,000 144 12 x 12
3,500 - 4,500 224 16 x 14
5,000 - 6,000 320 16 x 20
6,500 - 7,500 484 22 x 22
96
480
120
144
176
688
928
1,320
November 9, 1998 (Version 3.1)
7-3