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XC2V2000-6BG957C

更新时间： 2024-11-09 09:37:27
品牌 Logo 应用领域
赛灵思 - XILINX 栅
页数 文件大小 规格书
309页 2266K
描述
Field Programmable Gate Array, 2688 CLBs, 2000000 Gates, 820MHz, CMOS, PBGA957, FLIP CHIP, BGA-957

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XC2V2000-6BG957C 数据手册

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R
Virtex-II 1.5V  
Field-Programmable Gate Arrays  
0
0
DS031-1 (v1.9) September 26, 2002  
Advance Product Specification  
Summary of VirtexTM-II Features  
•
Industry First Platform FPGA Solution  
-
-
Programmable sink current (2 mA to 24 mA) per I/O  
Digitally Controlled Impedance (DCI) I/O: on-chip  
termination resistors for single-ended I/O standards  
•
IP-Immersion Architecture  
-
-
-
Densities from 40K to 8M system gates  
-
-
-
-
PCI-X compatible (133 MHz and 66 MHz) at 3.3V  
PCI compliant (66 MHz and 33 MHz) at 3.3V  
CardBus compliant (33 MHz) at 3.3V  
Differential Signaling  
420 MHz internal clock speed (Advance Data)  
840+ Mb/s I/O (Advance Data)  
•
•
SelectRAM™ Memory Hierarchy  
-
3 Mb of dual-port RAM in 18 Kbit block SelectRAM  
resources  
·
840 Mb/s Low-Voltage Differential Signaling I/O  
(LVDS) with current mode drivers  
-
Up to 1.5 Mb of distributed SelectRAM resources  
·
·
Bus LVDS I/O  
Lightning Data Transport (LDT) I/O with current  
driver buffers  
High-Performance Interfaces to External Memory  
-
DRAM interfaces  
·
Low-Voltage Positive Emitter-Coupled Logic  
(LVPECL) I/O  
Built-in DDR input and output registers  
·
·
·
SDR / DDR SDRAM  
Network FCRAM  
Reduced Latency DRAM  
·
-
Proprietary high-performance SelectLink  
Technology  
-
-
SRAM interfaces  
·
·
SDR / DDR SRAM  
QDR™ SRAM  
·
·
·
High-bandwidth data path  
Double Data Rate (DDR) link  
Web-based HDL generation methodology  
CAM interfaces  
•
•
Arithmetic Functions  
•
•
Supported by Xilinx Foundation™ and Alliance  
Series™ Development Systems  
-
-
Dedicated 18-bit x 18-bit multiplier blocks  
Fast look-ahead carry logic chains  
-
-
-
Integrated VHDL and Verilog design flows  
Compilation of 10M system gates designs  
Internet Team Design (ITD) tool  
Flexible Logic Resources  
-
Up to 93,184 internal registers / latches with Clock  
Enable  
SRAM-Based In-System Configuration  
-
Up to 93,184 look-up tables (LUTs) or cascadable  
16-bit shift registers  
-
-
Fast SelectMAP configuration  
Triple Data Encryption Standard (DES) security  
option (Bitstream Encryption)  
-
-
Wide multiplexers and wide-input function support  
Horizontal cascade chain and sum-of-products  
support  
-
-
-
-
IEEE 1532 support  
Partial reconfiguration  
Unlimited reprogrammability  
Readback capability  
-
Internal 3-state bussing  
•
High-Performance Clock Management Circuitry  
-
Up to 12 DCM (Digital Clock Manager) modules  
•
•
0.15 µm 8-Layer Metal Process with 0.12 µm  
High-Speed Transistors  
·
·
·
Precise clock de-skew  
Flexible frequency synthesis  
High-resolution phase shifting  
1.5V (V  
) Core Power Supply, Dedicated 3.3V  
CCINT  
-
16 global clock multiplexer buffers  
V
Auxiliary and V  
I/O Power Supplies  
CCO  
CCAUX  
•
•
Active Interconnect Technology  
•
•
IEEE 1149.1 Compatible Boundary-Scan Logic  
Support  
-
-
Fourth generation segmented routing structure  
Predictable, fast routing delay, independent of fanout  
Flip-Chip and Wire-Bond Ball Grid Array (BGA)  
Packages in Three Standard Fine Pitches (0.80 mm,  
1.00 mm, and 1.27 mm)  
SelectI/O™-Ultra Technology  
-
-
Up to 1,108 user I/Os  
•
100% Factory Tested  
19 single-ended and six differential standards  
© 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS031-1 (v1.9) September 26, 2002  
Advance Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
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