0
R
Virtex-II 1.5V
Field-Programmable Gate Arrays
0
0
DS031-1 (v1.9) September 26, 2002
Advance Product Specification
Summary of VirtexTM-II Features
•
Industry First Platform FPGA Solution
-
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Programmable sink current (2 mA to 24 mA) per I/O
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
•
IP-Immersion Architecture
-
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Densities from 40K to 8M system gates
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PCI-X compatible (133 MHz and 66 MHz) at 3.3V
PCI compliant (66 MHz and 33 MHz) at 3.3V
CardBus compliant (33 MHz) at 3.3V
Differential Signaling
420 MHz internal clock speed (Advance Data)
840+ Mb/s I/O (Advance Data)
•
•
SelectRAM™ Memory Hierarchy
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3 Mb of dual-port RAM in 18 Kbit block SelectRAM
resources
·
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
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Up to 1.5 Mb of distributed SelectRAM resources
·
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Bus LVDS I/O
Lightning Data Transport (LDT) I/O with current
driver buffers
High-Performance Interfaces to External Memory
-
DRAM interfaces
·
Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
Built-in DDR input and output registers
·
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SDR / DDR SDRAM
Network FCRAM
Reduced Latency DRAM
·
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Proprietary high-performance SelectLink
Technology
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SRAM interfaces
·
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SDR / DDR SRAM
QDR™ SRAM
·
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High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
CAM interfaces
•
•
Arithmetic Functions
•
•
Supported by Xilinx Foundation™ and Alliance
Series™ Development Systems
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Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
-
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Integrated VHDL and Verilog design flows
Compilation of 10M system gates designs
Internet Team Design (ITD) tool
Flexible Logic Resources
-
Up to 93,184 internal registers / latches with Clock
Enable
SRAM-Based In-System Configuration
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Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
-
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Fast SelectMAP configuration
Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
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Wide multiplexers and wide-input function support
Horizontal cascade chain and sum-of-products
support
-
-
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IEEE 1532 support
Partial reconfiguration
Unlimited reprogrammability
Readback capability
-
Internal 3-state bussing
•
High-Performance Clock Management Circuitry
-
Up to 12 DCM (Digital Clock Manager) modules
•
•
0.15 µm 8-Layer Metal Process with 0.12 µm
High-Speed Transistors
·
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Precise clock de-skew
Flexible frequency synthesis
High-resolution phase shifting
1.5V (V
) Core Power Supply, Dedicated 3.3V
CCINT
-
16 global clock multiplexer buffers
V
Auxiliary and V
I/O Power Supplies
CCO
CCAUX
•
•
Active Interconnect Technology
•
•
IEEE 1149.1 Compatible Boundary-Scan Logic
Support
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Fourth generation segmented routing structure
Predictable, fast routing delay, independent of fanout
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Three Standard Fine Pitches (0.80 mm,
1.00 mm, and 1.27 mm)
SelectI/O™-Ultra Technology
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Up to 1,108 user I/Os
•
100% Factory Tested
19 single-ended and six differential standards
© 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-1 (v1.9) September 26, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
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