Datasheet > XC2S50-5TQG144Q

XC2S50-5TQG144Q

更新时间： 2024-09-19 19:12:27

品牌	Logo	应用领域
赛灵思 - XILINX		栅可编程逻辑
页数	文件大小	规格书
4页	100K
描述
Field Programmable Gate Array, 384 CLBs, 50000 Gates, PQFP144, PLASTIC, TQFP-144

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XC2S50-5TQG144Q 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	144
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.25	JESD-30 代码：	S-PQFP-G144
JESD-609代码：	e3	长度：	20 mm
湿度敏感等级：	3	可配置逻辑块数量：	384
等效关口数量：	50000	端子数量：	144
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	384 CLBS, 50000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压：	2.625 V
最小供电电压：	2.375 V	标称供电电压：	2.5 V
表面贴装：	YES	温度等级：	AUTOMOTIVE
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	20 mm
Base Number Matches：	1

XC2S50-5TQG144Q 数据手册

— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —

Spartan-II 2.5V FPGA

Automotive IQ Product Family:

Introduction and Ordering

Product Specification

DS105-1 (v2.0) August 9, 2013

Introduction

The Spartan™-II 2.5V Field-Programmable Gate Array

(FPGA) Automotive IQ product family gives users high per-

formance, abundant logic resources, and a rich feature set.

The six-member family offers densities ranging from 15,000

to 200,000 system gates, as shown in Table 1.

•

System level features

SelectRAM+™ hierarchical memory:

16 bits/LUT distributed RAM

Configurable 4K-bit block RAM

Fast interfaces to external RAM

Fully PCI compliant

Spartan-II devices deliver more gates, I/Os, and features

per Dollar/Euro than other FPGAs by combining advanced

0.18 μm process technology with a streamlined

Virtex™-based architecture. Features include block RAM

(to 56K bits), distributed RAM (to 75,264 bits), 16 selectable

I/O standards, and four DLLs. Fast, predictable interconnect

means that successive design iterations continue to meet

timing requirements.

Low-power segmented routing architecture

Full readback ability for verification/observability

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input functions

Abundant registers/latches with enable, set, reset

Four dedicated DLLs for advanced clock control

Four primary low-skew global clock distribution nets

IEEE 1149.1 compatible boundary scan logic

The Spartan-II family is a superior alternative to mask-pro-

grammed ASICs. The FPGA avoids the initial cost, lengthy

development cycles, and inherent risk of conventional

ASICs. Also, FPGA programmability permits design

upgrades in the field with no hardware replacement neces-

sary (impossible with ASICs).

•

Versatile I/O and packaging

Family footprint compatibility in common packages

16 high-performance interface standards

Zero hold time simplifies system timing

Fully supported by powerful Xilinx development system

Foundation™ ISE Series: Fully integrated software

Alliance Series™: For use with third-party tools

Fully automatic mapping, placement, and routing

Features

•

Guaranteed to meet full electrical specifications over

T = –40°C to +125°C

•

Refer to Spartan-II 2.5V FPGA Detailed Functional

Description (DS001-2) for device functional description

•

Second generation ASIC replacement technology

Densities as high as 5,292 logic cells with up to

200,000 system gates

Other than the DC parameters listed, all other DC

specifications are the same as referenced in the

Spartan-II 2.5V FPGA DC and Switching

Characteristics (DS001-3) data sheet

Streamlined features based on Virtex architecture

Unlimited reprogrammability

•

Refer to Spartan-II 2.5V FPGA Pinout Tables

(DS001-4) for all pin descriptions

Table 1: Spartan-II FPGA Family Members

CLB

Array

(R x C)

Maximum

Total

Logic

Cells

System Gates

(Logic and RAM)

Total

Available

Distributed RAM Block RAM

(1)

Device

XC2S15

XC2S30

XC2S50

XC2S100

XC2S150

XC2S200

CLBs User I/O

Bits

16K

24K

32K

40K

48K

56K

432

15,000

30,000

8 x 12

12 x 18

16 x 24

20 x 30

24 x 36

28 x 42

216

384

600

864

1,176

6,144

972

132

176

284

13,824

24,576

38,400

55,296

75,264

1,728

2,700

3,888

5,292

50,000

100,000

150,000

200,000

Notes:

1. All user I/O counts do not include the four global clock/user input pins. See details in Table 3, page 3.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS105-1 (v2.0) August 9, 2013

www.xilinx.com

Product Specification

12 3 4

中文翻译

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与XC2S50-5TQG144Q相关器件

型号	品牌	获取价格	描述	数据表
XC2S50-5VQ100C	XILINX	获取价格	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S50-5VQ100I	XILINX	获取价格	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S50-5VQG100C	XILINX	获取价格	Spartan-II FPGA Family
XC2S50-5VQG100I	XILINX	获取价格	Spartan-II FPGA Family
XC2S50-6CS144C	XILINX	获取价格	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S50-6CS144I	XILINX	获取价格	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S50-6CSG144C	XILINX	获取价格	Spartan-II FPGA Family
XC2S50-6CSG144I	XILINX	获取价格	Spartan-II FPGA Family
XC2S50-6FG256C	XILINX	获取价格	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S50-6FG256I	XILINX	获取价格	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information

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