Datasheet > XC2C32-4PCG44I

XC2C32-4PCG44I

更新时间： 2024-11-11 08:05:51

品牌	Logo	应用领域
赛灵思 - XILINX		输入元件可编程逻辑
页数	文件大小	规格书
12页	76K
描述
Flash PLD, 4.5ns, CMOS, PQCC44, 17.50 X 17.50 MM, 1.27 MM PITCH, PLASTIC, LCC-44

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技术参数
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XC2C32-4PCG44I 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	44
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.69	其他特性：	FAST ZERO POWER DESIGN TECHNOLOGY
JESD-30 代码：	S-PQCC-J44	JESD-609代码：	e3
长度：	16.5862 mm	湿度敏感等级：	3
专用输入次数：	1	I/O 线路数量：	33
端子数量：	44	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	1 DEDICATED INPUTS, 33 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	245
可编程逻辑类型：	FLASH PLD	传播延迟：	4.5 ns
认证状态：	Not Qualified	座面最大高度：	4.57 mm
最大供电电压：	1.9 V	最小供电电压：	1.7 V
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	16.5862 mm

XC2C32-4PCG44I 数据手册

XC2C32 CoolRunner-II CPLD

DS091 (v1.0) June 4, 2002

Advance Product Specification

Features

Description

•

Optimized for 1.8V systems

The CoolRunner-II 32-macrocell device is designed for both

high performance and low power applications. This lends

power savings to high-end communication equipment and

high speed to battery operated devices. Due to the low

power stand-by and dynamic operation, overall system reli-

ability is improved

As fast as 3.5 ns pin-to-pin logic delays

As low as 14 µA quiescent current

32 macrocells with up to 800 logic gates

Fast input registers

Slew rate control on individual outputs

LVCMOS 1.8V through 3.3V

1.5V I/O compatible

This device consists of four Function Blocks inter-con-

nected by a low power Advanced Interconnect Matrix (AIM).

The AIM feeds 40 true and complement inputs to each

Function Block. The Function Blocks consist of a 40 by 56

P-term PLA and 16 macrocells which contain numerous

configuration bits that allow for combinational or registered

modes of operation.

LVTTL 3.3V

•

Available in multiple package options

44-pin PLCC with 33 user I/O

44-pin VQFP with 33 user I/O

56-ball CP BGA with 33 user I/O

Additionally, these registers can be globally reset or preset

and configured as a D or T flip-flop or as a D latch. There

are also multiple clock signals, both global and local product

term types, configured on a per macrocell basis. Output pin

configurations include slew rate limit, bus hold, pull-up,

open drain and programmable grounds. A Schmitt trigger

input is available on a per input pin basis. In addition to stor-

ing macrocell output states, the macrocell registers may be

configured as "fast input" registers to store signals directly

from input pins.

Advanced system features

Fastest in system programming

1.8V ISP using IEEE 1532 (JTAG) interface

IEEE1149.1 JTAG Boundary Scan Test

Optional Schmitt-trigger input (per pin)

FZP 100% CMOS product term generation

Flexible clocking modes

Optional DualEDGE triggered registers

Global signal options with macrocell control

Multiple global clocks with phase selection per

macrocell

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as

a synchronous clock source. Macrocell registers can be

individually configured to power up to the zero or one state.

A global set/reset control line is also available to asynchro-

nously set or reset selected registers during operation.

Additional local clock, synchronous clock-enable, asyncho-

nous set/reset and output enable signals can be formed

using product terms on a per-macrocell or per-Function

Block basis.

Multiple global output enables

Global set/reset

Efficient control term clocks, output enables and

set/resets for each macrocell and shared across

function blocks

Advanced design security

Open-drain output option for Wired-OR and LED

drive

Optional configurable grounds on unused I/Os

Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels

A DualEDGE flip-flop feature is also available on a per mac-

rocell basis. This feature allows high performance synchro-

nous operation based on lower frequency clocking to help

reduce the total power consumption of the device.

PLA architecture

Superior pinout retention

100% product term routability across function

block

The CoolRunner-II 32-macrocell CPLD is I/O compatible

with standard LVTTL and LVCMOS18, LVCMOS25, and

LVCMOS33 (see Table 1). This device is also 1.5V I/O com-

patible with the use of Schmitt-trigger inputs.

Hot pluggable

Refer to the CoolRunner™-II family data sheet for architec-

ture description.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS091 (v1.0) June 4, 2002

www.xilinx.com

Advance Product Specification

1-800-255-7778

12 3 4 5 6 7...12

中文翻译

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与XC2C32-4PCG44I相关器件

型号	品牌	获取价格	描述	数据表
XC2C32-4VQ44I	XILINX	获取价格	Flash PLD, 4.5ns, 32-Cell, CMOS, PQFP44, 12 X 12 MM, 0.80 MM PITCH, VQFP-44
XC2C32A	XILINX	获取价格	CoolRunner-II CPLD Family
XC2C32A-3CPG56C	XILINX	获取价格	暂无描述
XC2C32A-3VQG44C	XILINX	获取价格	Flash PLD, 3ns, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44
XC2C32A-4PC44C	XILINX	获取价格	暂无描述
XC2C32A-4QFG32C	XILINX	获取价格	Flash PLD, 4ns, 32-Cell, CMOS, PDSO32, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, QFN-32
XC2C32A-6CP56C	XILINX	获取价格	暂无描述
XC2C32A-6CPG56C	XILINX	获取价格	Flash PLD, 6ns, 32-Cell, CMOS, PBGA56, 6 X 6 MM, 0.50 MM PITCH, LEAD FREE, CSP-56
XC2C32A-6CPG56I	XILINX	获取价格	暂无描述
XC2C32A-6PCG44I	XILINX	获取价格	暂无描述

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