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XC2C256-7VQG100I PDF预览

XC2C256-7VQG100I

更新时间： 2024-09-19 03:53:39
品牌 Logo 应用领域
赛灵思 - XILINX 可编程逻辑器件输入元件PC
页数 文件大小 规格书
24页 422K
描述
CoolRunner-II CPLD

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中文翻译

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XC2C256-7VQG100I 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：TFQFP, TQFP100,.63SQ针数：100
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：0.94Samacsys Confidence：4
Samacsys Status：ReleasedSamacsys PartID：664812
Samacsys Pin Count：100Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Quad Flat PackagesSamacsys Footprint Name：VQFP-100
Samacsys Released Date：2017-03-13 10:48:05Is Samacsys：N
其他特性：REAL DIGITAL DESIGN TECHNOLOGY系统内可编程：YES
JESD-30 代码：S-PQFP-G100JESD-609代码：e3
JTAG BST：YES长度：14 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：80宏单元数：256
端子数量：100最高工作温度：85 °C
最低工作温度：-40 °C组织：0 DEDICATED INPUTS, 80 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP100,.63SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：1.5/3.3,1.8 V
可编程逻辑类型：FLASH PLD传播延迟：7.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Programmable Logic Devices最大供电电压：1.9 V
最小供电电压：1.7 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

XC2C256-7VQG100I 数据手册

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XC2C256 CoolRunner-II CPLD  
0
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DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
Features  
Description  
•
Optimized for 1.8V systems  
The CoolRunner™-II 256-macrocell device is designed for  
both high performance and low power applications. This  
lends power savings to high-end communication equipment  
and high speed to battery operated devices. Due to the low  
power stand-by and dynamic operation, overall system reli-  
ability is improved  
-
-
As fast as 5.7 ns pin-to-pin delays  
As low as 13 µA quiescent current  
•
Industry’s best 0.18 micron CMOS CPLD  
-
Optimized architecture for effective logic synthesis.  
Refer to the CoolRunner™-II family data sheet for  
architecture description.  
This device consists of sixteen Function Blocks inter-con-  
nected by a low power Advanced Interconnect Matrix (AIM).  
The AIM feeds 40 true and complement inputs to each  
Function Block. The Function Blocks consist of a 40 by 56  
P-term PLA and 16 macrocells which contain numerous  
configuration bits that allow for combinational or registered  
modes of operation.  
-
Multi-voltage I/O operation — 1.5V to 3.3V  
•
•
Available in multiple package options  
-
-
-
-
-
-
100-pin VQFP with 80 user I/O  
144-pin TQFP with 118 user I/O  
132-ball CP (0.5mm) BGA with 106 user I/O  
208-pin PQFP with 173 user I/O  
256-ball FT (1.0mm) BGA with 184 user I/O  
Pb-free available for all packages  
Additionally, these registers can be globally reset or preset  
and configured as a D or T flip-flop or as a D latch. There  
are also multiple clock signals, both global and local product  
term types, configured on a per macrocell basis. Output pin  
configurations include slew rate limit, bus hold, pull-up,  
open drain and programmable grounds. A Schmitt-trigger  
input is available on a per input pin basis. In addition to stor-  
ing macrocell output states, the macrocell registers may be  
configured as "direct input" registers to store signals directly  
from input pins.  
Advanced system features  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
·
-
-
-
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt-trigger input (per pin)  
Unsurpassed low power management  
·
DataGATE enable (DGE) signal control  
-
-
-
Two separate I/O banks  
RealDigital 100% CMOS product term generation  
Flexible clocking modes  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as  
a synchronous clock source. Macrocell registers can be  
individually configured to power up to the zero or one state.  
A global set/reset control line is also available to asynchro-  
nously set or reset selected registers during operation.  
Additional local clock, synchronous clock-enable, asynchro-  
nous set/reset and output enable signals can be formed  
using product terms on a per-macrocell or per-Function  
Block basis.  
·
·
·
Optional DualEDGE triggered registers  
Clock divider (divide by 2,4,6,8,10,12,14,16)  
CoolCLOCK  
-
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
·
·
Multiple global output enables  
Global set/reset  
-
-
Advanced design security  
PLA architecture  
A DualEDGE flip-flop feature is also available on a per mac-  
rocell basis. This feature allows high performance synchro-  
nous operation based on lower frequency clocking to help  
reduce the total power consumption of the device.  
·
·
Superior pinout retention  
100% product term routability across function  
block  
-
-
Open-drain output option for Wired-OR and LED  
drive  
Optional bus-hold, 3-state or weak pull-up on  
selected I/O pins  
Optional configurable grounds on unused I/Os  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels  
Circuitry has also been included to divide one externally  
supplied global clock (GCK2) by eight different selections.  
This yields divide by even and odd clock frequencies.  
The use of the clock divide (division by 2) and DualEDGE  
flip-flop gives the resultant CoolCLOCK feature.  
-
-
DataGATE is a method to selectively disable inputs of the  
CPLD that are not of interest during certain points in time.  
·
SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility  
-
Hot pluggable  
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
1
Preliminary Product Specification  
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中文翻译

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XC2C256-7VQG100I 替代型号

型号 品牌 替代类型 描述 数据表
XC2C256-7VQG100C XILINX

完全替代

 CoolRunner-II CPLD
XC2C256-6VQG100C XILINX

完全替代

 CoolRunner-II CPLD
XC2C256-7VQ100I XILINX

完全替代

 CoolRunner-II CPLD

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