Datasheet > XAM3352ZCZA27

XAM3352ZCZA27

更新时间： 2024-11-27 07:56:43

品牌	Logo	应用领域
德州仪器 - TI		微处理器
页数	文件大小	规格书
162页	1837K
描述
AM335x ARM Cortex-A8 Microprocessors (MPUs)

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XAM3352ZCZA27 数据手册

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

www.ti.com

SPRS717 –OCTOBER 2011

AM335x ARM^®Cortex™-A8 Microprocessors (MPUs)

Check for Samples: AM3359, AM3358

1 Device Summary

1.1 Features

1234567

– 256KB of L2 Cache with Error Correcting

• Highlights

– 500-MHz, 600-MHz, or 720-MHz ARM^®

Cortex™-A8 32-Bit RISC Microprocessor

Code (ECC)

– 176KB of On-Chip Boot ROM

– 64KB of Dedicated RAM

– Emulation/Debug

•

NEON™ SIMD Coprocessor

32KB/32KB of L1 Instruction/Data Cache

with Single-Error Detection (parity)

•

JTAG

•

256KB of L2 Cache with Error Correcting

Code (ECC)

Embedded Trace Module

Embedded Trace Buffer

– mDDR(LPDDR)/DDR2/DDR3 Support

– Interrupt Controller (up to 128 interrupt

– General-Purpose Memory Support (NAND,

NOR, SRAM, etc.) Supporting Up to 16-bit

ECC

requests)

• On-Chip Memory (Shared L3 RAM)

– 64 KB of General-Purpose On-Chip Memory

– SGX530 Graphics Engine

Controller (OCMC) RAM

– Programmable Real-Time Unit Subsystem

– Real-Time Clock (RTC)

– Up to Two USB 2.0 High-Speed OTG Ports

with Integrated PHY

– 10/100/1000 Ethernet Switch Supporting Up

to Two Ports

– Two Controller Area Network Ports (CAN)

– Six UARTs, Two McASPs, Two McSPI, and

Two I2C Ports

– 12-Bit Successive Approximation Register

(SAR) ADC

– Up to Three 32-Bit Enhanced Capture

Modules (eCAP)

– Up to Three Enhanced High-Resolution PWM

Modules (eHRPWM)

– Crypto Hardware Accelerators (AES, SHA,

– Accessible to all Masters

– Supports Retention for Fast Wake-Up

• External Memory Interfaces (EMIF)

– mDDR/DDR2/DDR3 Controller:

•

mDDR: 200-MHz Clock (400-MHz Data

Rate)

DDR2: 266-MHz Clock (532-MHz Data

Rate)

DDR3: 303-MHz Clock (606-MHz Data

Rate)

•

16-Bit Data Bus

1 GB of Total Addressable Space

Supports One x16, Two x8, or Four x4

Memory Device Configurations

•

Supports Retention for Fast Wake-Up

– General-Purpose Memory Controller (GPMC)

PKA, RNG)

•

Flexible 8/16-Bit Asynchronous Memory

Interface with Up to seven Chip Selects

(NAND, NOR, Muxed-NOR, SRAM, etc.)

• MPU Subsystem

– 500-MHz, 600-MHz, or 720-MHz ARM^®

Cortex™-A8 32-Bit RISC Microprocessor

•

Uses BCH Code to Support 4-Bit, 8-Bit, or

16-Bit ECC

Uses Hamming Code to Support 1-Bit

ECC

– NEON™ SIMD Coprocessor

– 32KB of L1 Instruction Cache with

Single-Error Detection (parity)

– 32KB of L1 Data Cache with Single

– Error Locator Module (ELM)

•

Used in Conjunction with the GPMC to

Locate Addresses of Data Errors from

Error-Detection (parity)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SmartReflex, DSP/BIOS, XDS are trademarks of Texas Instruments.

Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.

ARM is a registered trademark of ARM Ltd or its subsidiaries.

EtherCAT is a registered trademark of EtherCAT Technology Group.

POWERVR is a registered trademark of Imagination Technologies Limited.

All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the formative or design phase of

development. Characteristic data and other specifications are design goals. Texas

Instruments reserves the right to change or discontinue these products without notice.

ProdPrev

English Data Sheet: SPRS717

12 3 4 5 6 7...162

中文翻译

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