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Spartan-3 Automotive
XA FPGA Family:
Introduction and Ordering
Product Specification
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DS314-1 (v1.2.1) November 28, 2006
Summary
The Xilinx Automotive (XA) Spartan™-3 family of Field-Programmable Gate Arrays meets the needs of high-volume,
cost-sensitive automotive electronic applications. The five-member family offers densities ranging from 50,000 to 1.5 million
system gates, as shown in Table 1.
Introduction
Features
•
AEC-Q100 device qualification and full PPAP
documentation support available in both extended
temperature Q-grade and I-grade
XA devices are available in both extended-temperature
Q-grade (-40°C to +125°C Tj) and I-grade (-40°C to +100°C
Tj) and are qualified to the industry-recognized AEC-Q100
standard.
•
Guaranteed to meet full electrical specification over the
TJ=-40°C to +125°C temperature range
The XA Spartan-3 family builds on the success of the earlier
XA Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. These Spartan-3
enhancements, combined with advanced process
technology, deliver more functionality and bandwidth per
dollar than was previously possible, setting new standards
in the programmable logic industry.
•
•
Revolutionary 90-nanometer process technology
Low cost, high-performance logic solution for
high-volume, automotive applications
♦
Three power rails: for core (1.2V), I/Os (1.2V to
3.3V), and auxiliary purposes (2.5V)
•
SelectIO™ signaling
♦
♦
♦
♦
♦
♦
♦
Up to 487 I/O pins
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of advanced automotive
electronics modules and systems ranging from the latest
driver assistance and infotainment systems to instrument
clusters and gateways.
622 Mb/s data transfer rate per I/O
Eighteen single-ended signal standards
Eight differential signal standards including LVDS
Termination by Digitally Controlled Impedance
Signal swing ranging from 1.14V to 3.45V
Double Data Rate (DDR) support
The Spartan-3 family is a flexible alternative to ASICs,
ASSPs, and microcontrollers. FPGAs avoid the high initial
NREs, the lengthy development cycles, and problems with
obsolescence. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement
necessary.
•
Logic resources
♦
♦
Abundant logic cells with shift register capability
Wide multiplexers
Table 1: Summary of Spartan-3 FPGA Attributes
CLB Array
(One CLB = Four Slices)
Maximum
Maximum Differential
System
Gates
Logic
Cells
Distributed BlockRAM
Dedicated
Multipliers
Device
XA3S50
Rows Columns Total CLBs RAM (bits1)
(bits1)
124K
173K
264K
333K
576K
DCMs
User I/O
I/O Pairs
50K
200K
400K
1M
1,728
4,320
16
24
32
48
64
12
20
28
40
52
192
480
12K
30K
4
2
4
4
4
4
124
56
XA3S200
XA3S400
XA3S1000
XA3S1500
Notes:
12
16
24
32
173
76
8,064
896
56K
264
116
17,280
29,952
1,920
3,328
120K
208K
391
175
1.5M
487
221
1. By convention, one Kb is equivalent to 1,024 bits.
© 2004, 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS314-1 (v1.2.1) November 28, 2006
www.xilinx.com
Product Specification
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