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X9271

更新时间: 2024-11-03 14:57:23
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
19页 790K
描述
Single Digitally-Controlled (XDCP?) Potentiometer

X9271 数据手册

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DATASHEET  
X9271  
FN8174  
Rev 5.00  
October 15, 2015  
Single Supply/Low Power/256-Tap/SPI Bus Single, Digitally Controlled (XDCP™)  
Potentiometer  
The X9271 integrates a single, digitally controlled  
potentiometer (XDCP™) on a monolithic CMOS integrated  
circuit.  
Features  
• 256 Resistor Taps  
• SPI Serial Interface for Write, Read, and Transfer  
Operations of Potentiometer  
The digitally controlled potentiometer is implemented by  
using 255 resistive elements in a series array. Between each  
element are tap points connected to the wiper terminal  
through switches. The position of the wiper on the array is  
controlled by the user through the SPI bus interface. The  
potentiometer has associated with it a volatile Wiper Counter  
Register (WCR) and four nonvolatile data registers that can  
be directly written to and read by the user. The contents of  
the WCR control the position of the wiper on the resistor  
array though the switches. Power-up recalls the contents of  
the default data register (DR0) to the WCR.  
• Wiper Resistance, 100Ω typical at V  
• 16 Nonvolatile Data Registers  
= 5V  
CC  
• Nonvolatile Storage of Multiple Wiper Positions  
• Power-on Recall; Loads Saved Wiper Position on  
Power-up  
• Standby Current <3µA Max  
• V  
CC  
= 2.7V to 5.5V Operation  
• 50kΩ End-to-End Resistance  
• 100-yr Data Retention  
The XDCP can be used as a three-terminal potentiometer or  
as a two-terminal variable resistor in a wide variety of  
applications including control, parameter adjustments, and  
signal processing.  
• Endurance: 100,000 Data Changes per Bit per Register  
• 14-Lead TSSOP  
• Low-power CMOS  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
Functional Diagram  
V
R
H
CC  
WRITE  
READ  
50kΩ  
256 TAPS  
ADDRESS  
DATA  
STATUS  
TRANSFER  
INC/DEC  
POWER-ON RECALL  
WIPER COUNTER  
REGISTER (WCR)  
BUS  
INTERFACE  
AND CONTROL  
SPI  
BUS  
INTERFACE  
POT  
DATA REGISTERS  
16 Bytes  
CONTROL  
R
V
R
W
SS  
L
FN8174 Rev 5.00  
October 15, 2015  
Page 1 of 19  

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