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X9259UB24 PDF预览

X9259UB24

更新时间: 2024-11-28 22:17:47
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XICOR /
页数 文件大小 规格书
25页 402K
描述
Quad Digitally-Controlled (XDCP) Potentiometers

X9259UB24 数据手册

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APPLICATION NOTES AND DEVELOPMENT SYSTEM  
A V A I L A B L E  
AN99 • AN115 • AN124 •AN133 • AN134 • AN135  
Single Supply / Low Power / 256-tap / 2-Wire bus  
X9259  
Quad Digitally-Controlled (XDCPTM) Potentiometers  
FEATURES  
DESCRIPTION  
• Quad–Four separate potentiometers  
• 256 resistor taps/pot–0.4% resolution  
• 2-Wire Serial Interface for write, read, and  
transfer operations of the potentiometer  
The X9259 integrates  
potentiometer (XDCP) on  
integrated circuit.  
4
digitally controlled  
monolithic CMOS  
a
The digital controlled potentiometer is implemented  
using 255 resistive elements in a series array. Between  
each element are tap points connected to the wiper  
terminal through switches. The position of the wiper on  
the array is controlled by the user through the 2-Wire  
bus interface. Each potentiometer has associated with  
it a volatile Wiper Counter Register (WCR) and a four  
nonvolatile Data Registers that can be directly written  
to and read by the user. The contents of the WCR  
controls the position of the wiper on the resistor array  
though the switches. Powerup recalls the contents of  
the default Data Register (DR0) to the WCR.  
• Wiper Resistance, 100typical @ V  
= 5V  
CC  
• 4 Nonvolatile Data Registers for Each  
Potentiometer  
• Nonvolatile Storage of Multiple Wiper Positions  
• Power On Recall. Loads SavedWiper Position on  
Power Up.  
• Standby Current < 5µA Max  
• V : 2.7V to 5.5V Operation  
CC  
• 50K, 100Kversions of End to End Pot  
Resistance  
• Endurance: 100,000 Data Changes per Bit per  
Register  
• 100 yr. Data Retention  
The XDCP can be used as  
a three-terminal  
• Single Supply Version of X9258  
• 24-Lead SOIC, 24-Lead TSSOP, 24-Lead XBGA  
• Low Power CMOS  
potentiometer or as a two terminal variable resistor in  
a wide variety of applications including control,  
parameter adjustments, and signal processing.  
FUNCTIONAL DIAGRAM  
V
R
R
R
R
H3  
CC  
H0  
H1  
H2  
Write  
Read  
Address  
Data  
Status  
Transfer  
Inc/Dec  
Power On Recall  
Bus  
2-Wire  
Bus  
Interface  
Wiper Counter  
Registers (WCR)  
Interface  
and Control  
Data Registers  
16 Bytes  
Control  
V
R
R
R
R
R
R
R
R
L3  
SS  
W0  
L0  
W1  
L1 W2  
L2 W3  
50Kor 100Kversions  
Characteristics subject to change without notice. 1 of 25  
REV 1.2.3 4/30/02  
www.xicor.com  

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