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X9251

更新时间: 2024-11-20 14:58:11
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21页 988K
描述
Quad Digitally-Controlled (XDCP?) Potentiometer

X9251 数据手册

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DATASHEET  
X9251  
FN8166  
Rev 7.00  
January 14, 2021  
Single Supply/Low Power/256-Tap/SPI Bus, Quad Digitally-Controlled (XDCP™)  
Potentiometer  
The X9251 integrates four digitally controlled potentiometers  
Features  
(XDCP) on a monolithic CMOS integrated circuit.  
• Four potentiometers in one package  
The digitally controlled potentiometers are implemented with  
a combination of resistor elements and CMOS switches. The  
position of the wipers are controlled by the user through the  
SPI bus interface. Each potentiometer has associated with it a  
volatile Wiper Counter Register (WCR) and four nonvolatile  
Data Registers that can be directly written to and read by the  
user. The content of the WCR controls the position of the wiper.  
At power-up, the device recalls the content of the default Data  
Registers of each DCP (DR00, DR10, DR20, and DR30) to the  
corresponding WCR.  
• 256 resistor taps–0.4% resolution  
• SPI serial interface for write, read, and transfer operations of  
the potentiometer  
• Wiper resistance: 100Ω typical at V = 5V  
CC  
• 4 Nonvolatile data registers for each potentiometer  
• Nonvolatile storage of multiple wiper positions  
• Standby current <5µA max  
• V : 2.7V to 5.5V operation  
CC  
The XDCP can be used as a three terminal potentiometer or as  
a two terminal variable resistor in a wide variety of  
applications including control, parameter adjustments, and  
signal processing.  
• 50kΩ version of total resistance  
• 100 year data retention  
• Single supply version of X9250  
• Endurance: 100,000 data changes per bit per register  
• 24 Ld TSSOP  
• Low power CMOS  
• Pb-free (RoHS compliant)  
R
R
H3  
R
R
V
H1  
H2  
H0  
CC  
HOLD  
DCP1  
DCP3  
DCP2  
DCP0  
WCR1  
DR10  
DR11  
DR12  
DR13  
WCR3  
DR30  
DR31  
DR32  
DR33  
WCR2  
DR20  
DR21  
DR22  
DR23  
WCR0  
DR00  
DR01  
DR02  
DR03  
A1  
A0  
SO  
SI  
SPI  
Interface  
POWER UP,  
INTERFACE  
CONTROL  
AND  
STATUS  
SCK  
CS  
V
R
R
L3  
R
R
SS  
R
R
W3  
R
WP  
R
W0  
L1  
L2  
L0  
W1  
W2  
FIGURE 1. FUNCTIONAL DIAGRAM  
FN8166 Rev 7.00  
January 14, 2021  
Page 1 of 20  

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