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X9111TV14I-2.7 PDF预览

X9111TV14I-2.7

更新时间: 2024-09-24 21:19:39
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瑞萨 - RENESAS /
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19页 795K
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X9111TV14I-2.7 数据手册

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DATASHEET  
X9111  
FN8159  
Rev 5.00  
October 13, 2016  
Single Supply/Low Power/1024-Tap/SPI Bus/Single Digitally-Controlled (XDCP™)  
Potentiometer  
The X9111 integrates a single, digitally controlled  
Features  
potentiometer (XDCP) on a monolithic CMOS integrated circuit.  
• 1024 resistor taps – 10-bit resolution  
The digital controlled potentiometer is implemented using  
1023 resistive elements in a series array. Between each  
element are tap points connected to the wiper terminal  
through switches. The position of the wiper on the array is  
controlled by the user through the SPI bus interface. The  
potentiometer has associated with it a volatile Wiper Counter  
Register (WCR) and four nonvolatile Data Registers that can be  
directly written to and read by the user. The contents of the  
WCR control the position of the wiper on the resistor array  
through the switches. Power-up recalls the contents of the  
default data register (DR0) to the WCR.  
• SPI serial interface for write, read, and transfer operations of  
the potentiometer  
• Wiper resistance, 40Ω typical at 5V  
• Four nonvolatile Data Registers  
• Nonvolatile storage of multiple wiper positions  
• Power-on recall, loads saved wiper position on power-up  
• Standby current <3µA maximum  
• V : 2.7V to 5.5V operation  
CC  
• 100kΩ end-to-end resistance  
• 100-year data retention  
The XDCP can be used as a 3-terminal potentiometer or as a  
2-terminal variable resistor in a wide variety of applications  
including control, parameter adjustments, and signal  
processing.  
• Endurance: 100,000 data changes per bit per register  
• 14 Ld TSSOP  
• Low-power CMOS  
• Single supply version of the X9110  
• Pb-Free (RoHS compliant)  
V
R
H
CC  
WRITE  
READ  
TRANSFER  
ADDRESS  
DATA  
STATUS  
POWER-ON RECALL  
100kΩ  
1024-taps  
POT  
WIPER COUNTER  
REGISTER (WCR)  
BUS  
INTERFACE  
AND  
SPI  
BUS  
INTERFACE  
WIPER  
DATA REGISTERS  
CONTROL  
(DR0-DR3)  
CONTROL  
R
R
V
NC  
W
L
SS  
FIGURE 1. FUNCTIONAL DIAGRAM  
FN8159 Rev 5.00  
October 13, 2016  
Page 1 of 19  

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